James Zhu d0e62855fa drm/amdgpu: add uvd enc registers in header ... Add UVD encode write/read/size/base registers definition for uvd6.3 HEVC ecoding Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-10-06 17:43:53 -04:00
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uvd_4_0_d.h	drm/amd/amdgpu: Introduction of SI registers (v2)	2016-11-11 10:21:07 -05:00
uvd_4_0_sh_mask.h	drm/amd/amdgpu: Introduction of SI registers (v2)	2016-11-11 10:21:07 -05:00
uvd_4_2_d.h	drm/amdgpu: add support for UVD_NO_OP register	2016-08-24 16:25:04 -04:00
uvd_4_2_sh_mask.h	…
uvd_5_0_d.h	drm/amdgpu: switch UVD code to use UVD_NO_OP for padding	2016-08-24 16:25:05 -04:00
uvd_5_0_enum.h	…
uvd_5_0_sh_mask.h	…
uvd_6_0_d.h	drm/amdgpu: add uvd enc registers in header	2017-10-06 17:43:53 -04:00
uvd_6_0_enum.h	drm/amdgpu: add UVD 6.0 register headers	2015-06-03 21:03:08 -04:00
uvd_6_0_sh_mask.h	drm/amdgpu: add UVD 6.0 register headers	2015-06-03 21:03:08 -04:00