167 lines
4.6 KiB
C
167 lines
4.6 KiB
C
/*
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* Copyright (C) STMicroelectronics 2009
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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* Author: Sundar Iyer <sundar.iyer@stericsson.com>
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*
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* License Terms: GNU General Public License v2
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*
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* PRCM Unit registers
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*/
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#ifndef __DB8500_PRCMU_REGS_H
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#define __DB8500_PRCMU_REGS_H
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#include <linux/bitops.h>
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#include <mach/hardware.h>
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#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
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#define PRCM_ARM_PLLDIVPS 0x118
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#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE BITS(0, 5)
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#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xF
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#define PRCM_PLLARM_LOCKP 0x0A8
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#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 BIT(1)
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#define PRCM_ARM_CHGCLKREQ 0x114
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#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
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#define PRCM_PLLARM_ENABLE 0x98
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE BIT(0)
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#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON BIT(8)
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#define PRCM_ARMCLKFIX_MGT 0x0
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#define PRCM_A9_RESETN_CLR 0x1f4
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#define PRCM_A9_RESETN_SET 0x1f0
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#define PRCM_ARM_LS_CLAMP 0x30C
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#define PRCM_SRAM_A9 0x308
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY 0x130
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#define PRCM_IOCR 0x310
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#define PRCM_IOCR_IOFORCE BIT(0)
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/* CPU mailbox registers */
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#define PRCM_MBOX_CPU_VAL 0x0FC
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#define PRCM_MBOX_CPU_SET 0x100
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/* Dual A9 core interrupt management unit registers */
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#define PRCM_A9_MASK_REQ 0x328
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#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ BIT(0)
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#define PRCM_A9_MASK_ACK 0x32C
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#define PRCM_ARMITMSK31TO0 0x11C
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#define PRCM_ARMITMSK63TO32 0x120
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#define PRCM_ARMITMSK95TO64 0x124
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#define PRCM_ARMITMSK127TO96 0x128
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#define PRCM_POWER_STATE_VAL 0x25C
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#define PRCM_ARMITVAL31TO0 0x260
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#define PRCM_ARMITVAL63TO32 0x264
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#define PRCM_ARMITVAL95TO64 0x268
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#define PRCM_ARMITVAL127TO96 0x26C
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#define PRCM_HOSTACCESS_REQ 0x334
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#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ BIT(0)
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#define PRCM_ARM_IT1_CLR 0x48C
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#define PRCM_ARM_IT1_VAL 0x494
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#define PRCM_ITSTATUS0 0x148
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#define PRCM_ITSTATUS1 0x150
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#define PRCM_ITSTATUS2 0x158
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#define PRCM_ITSTATUS3 0x160
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#define PRCM_ITSTATUS4 0x168
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#define PRCM_ITSTATUS5 0x484
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#define PRCM_ITCLEAR5 0x488
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#define PRCM_ARMIT_MASKXP70_IT 0x1018
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/* System reset register */
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#define PRCM_APE_SOFTRST 0x228
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/* Level shifter and clamp control registers */
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#define PRCM_MMIP_LS_CLAMP_SET 0x420
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#define PRCM_MMIP_LS_CLAMP_CLR 0x424
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/* PRCMU HW semaphore */
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#define PRCM_SEM 0x400
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#define PRCM_SEM_PRCM_SEM BIT(0)
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/* PRCMU clock/PLL/reset registers */
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#define PRCM_PLLDSI_FREQ 0x500
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#define PRCM_PLLDSI_ENABLE 0x504
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#define PRCM_PLLDSI_LOCKP 0x508
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#define PRCM_DSI_PLLOUT_SEL 0x530
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#define PRCM_DSITVCLK_DIV 0x52C
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#define PRCM_APE_RESETN_SET 0x1E4
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#define PRCM_APE_RESETN_CLR 0x1E8
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#define PRCM_TCR 0x1C8
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#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
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#define PRCM_TCR_STOP_TIMERS BIT(16)
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#define PRCM_TCR_DOZE_MODE BIT(17)
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#define PRCM_CLKOCR 0x1CC
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#define PRCM_CLKOCR_CLKODIV0_SHIFT 0
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#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
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#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
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#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
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#define PRCM_CLKOCR_CLKODIV1_SHIFT 16
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#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
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#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
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#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
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#define PRCM_CLKOCR_CLK1TYPE BIT(28)
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#define PRCM_SGACLK_MGT 0x014
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#define PRCM_UARTCLK_MGT 0x018
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#define PRCM_MSP02CLK_MGT 0x01C
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#define PRCM_MSP1CLK_MGT 0x288
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#define PRCM_I2CCLK_MGT 0x020
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#define PRCM_SDMMCCLK_MGT 0x024
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#define PRCM_SLIMCLK_MGT 0x028
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#define PRCM_PER1CLK_MGT 0x02C
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#define PRCM_PER2CLK_MGT 0x030
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#define PRCM_PER3CLK_MGT 0x034
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#define PRCM_PER5CLK_MGT 0x038
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#define PRCM_PER6CLK_MGT 0x03C
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#define PRCM_PER7CLK_MGT 0x040
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#define PRCM_LCDCLK_MGT 0x044
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#define PRCM_BMLCLK_MGT 0x04C
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#define PRCM_HSITXCLK_MGT 0x050
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#define PRCM_HSIRXCLK_MGT 0x054
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#define PRCM_HDMICLK_MGT 0x058
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#define PRCM_APEATCLK_MGT 0x05C
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#define PRCM_APETRACECLK_MGT 0x060
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#define PRCM_MCDECLK_MGT 0x064
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#define PRCM_IPI2CCLK_MGT 0x068
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#define PRCM_DSIALTCLK_MGT 0x06C
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#define PRCM_DMACLK_MGT 0x074
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#define PRCM_B2R2CLK_MGT 0x078
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#define PRCM_TVCLK_MGT 0x07C
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#define PRCM_UNIPROCLK_MGT 0x278
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#define PRCM_SSPCLK_MGT 0x280
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#define PRCM_RNGCLK_MGT 0x284
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#define PRCM_UICCCLK_MGT 0x27C
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#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
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#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
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#define PRCM_CLK_MGT_CLKEN BIT(8)
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/* ePOD and memory power signal control registers */
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#define PRCM_EPOD_C_SET 0x410
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#define PRCM_SRAM_LS_SLEEP 0x304
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/* Debug power control unit registers */
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#define PRCM_POWER_STATE_SET 0x254
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/* Miscellaneous unit registers */
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#define PRCM_DSI_SW_RESET 0x324
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#define PRCM_GPIOCR 0x138
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/* GPIOCR register */
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#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
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#define PRCM_DDR_SUBSYS_APE_MINBW 0x438
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#endif /* __DB8500_PRCMU_REGS_H */
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