443 lines
10 KiB
C
443 lines
10 KiB
C
/* memctrlr.c: Driver for UltraSPARC-III memory controller.
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*
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* Copyright (C) 2001, 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <asm/spitfire.h>
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#include <asm/chmctrl.h>
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#include <asm/cpudata.h>
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#include <asm/oplib.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#define CHMCTRL_NDGRPS 2
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#define CHMCTRL_NDIMMS 4
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#define DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
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/* OBP memory-layout property format. */
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struct obp_map {
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unsigned char dimm_map[144];
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unsigned char pin_map[576];
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};
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#define DIMM_LABEL_SZ 8
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struct obp_mem_layout {
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/* One max 8-byte string label per DIMM. Usually
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* this matches the label on the motherboard where
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* that DIMM resides.
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*/
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char dimm_labels[DIMMS_PER_MC][DIMM_LABEL_SZ];
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/* If symmetric use map[0], else it is
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* asymmetric and map[1] should be used.
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*/
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char symmetric;
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struct obp_map map[2];
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};
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#define CHMCTRL_NBANKS 4
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struct bank_info {
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struct mctrl_info *mp;
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int bank_id;
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u64 raw_reg;
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int valid;
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int uk;
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int um;
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int lk;
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int lm;
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int interleave;
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unsigned long base;
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unsigned long size;
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};
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struct mctrl_info {
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struct list_head list;
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int portid;
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struct obp_mem_layout layout_prop;
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int layout_size;
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void __iomem *regs;
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u64 timing_control1;
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u64 timing_control2;
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u64 timing_control3;
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u64 timing_control4;
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u64 memaddr_control;
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struct bank_info logical_banks[CHMCTRL_NBANKS];
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};
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static LIST_HEAD(mctrl_list);
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/* Does BANK decode PHYS_ADDR? */
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static int bank_match(struct bank_info *bp, unsigned long phys_addr)
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{
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unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
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unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
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/* Bank must be enabled to match. */
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if (bp->valid == 0)
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return 0;
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/* Would BANK match upper bits? */
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upper_bits ^= bp->um; /* What bits are different? */
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upper_bits = ~upper_bits; /* Invert. */
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upper_bits |= bp->uk; /* What bits don't matter for matching? */
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upper_bits = ~upper_bits; /* Invert. */
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if (upper_bits)
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return 0;
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/* Would BANK match lower bits? */
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lower_bits ^= bp->lm; /* What bits are different? */
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lower_bits = ~lower_bits; /* Invert. */
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lower_bits |= bp->lk; /* What bits don't matter for matching? */
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lower_bits = ~lower_bits; /* Invert. */
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if (lower_bits)
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return 0;
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/* I always knew you'd be the one. */
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return 1;
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}
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/* Given PHYS_ADDR, search memory controller banks for a match. */
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static struct bank_info *find_bank(unsigned long phys_addr)
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{
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struct list_head *mctrl_head = &mctrl_list;
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struct list_head *mctrl_entry = mctrl_head->next;
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for (;;) {
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struct mctrl_info *mp =
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list_entry(mctrl_entry, struct mctrl_info, list);
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int bank_no;
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if (mctrl_entry == mctrl_head)
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break;
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mctrl_entry = mctrl_entry->next;
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for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
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struct bank_info *bp;
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bp = &mp->logical_banks[bank_no];
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if (bank_match(bp, phys_addr))
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return bp;
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}
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}
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return NULL;
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}
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/* This is the main purpose of this driver. */
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#define SYNDROME_MIN -1
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#define SYNDROME_MAX 144
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int chmc_getunumber(int syndrome_code,
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unsigned long phys_addr,
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char *buf, int buflen)
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{
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struct bank_info *bp;
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struct obp_mem_layout *prop;
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int bank_in_controller, first_dimm;
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bp = find_bank(phys_addr);
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if (bp == NULL ||
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syndrome_code < SYNDROME_MIN ||
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syndrome_code > SYNDROME_MAX) {
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buf[0] = '?';
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buf[1] = '?';
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buf[2] = '?';
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buf[3] = '\0';
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return 0;
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}
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prop = &bp->mp->layout_prop;
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bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
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first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
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first_dimm *= CHMCTRL_NDIMMS;
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if (syndrome_code != SYNDROME_MIN) {
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struct obp_map *map;
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int qword, where_in_line, where, map_index, map_offset;
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unsigned int map_val;
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/* Yaay, single bit error so we can figure out
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* the exact dimm.
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*/
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if (prop->symmetric)
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map = &prop->map[0];
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else
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map = &prop->map[1];
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/* Covert syndrome code into the way the bits are
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* positioned on the bus.
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*/
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if (syndrome_code < 144 - 16)
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syndrome_code += 16;
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else if (syndrome_code < 144)
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syndrome_code -= (144 - 7);
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else if (syndrome_code < (144 + 3))
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syndrome_code -= (144 + 3 - 4);
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else
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syndrome_code -= 144 + 3;
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/* All this magic has to do with how a cache line
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* comes over the wire on Safari. A 64-bit line
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* comes over in 4 quadword cycles, each of which
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* transmit ECC/MTAG info as well as the actual
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* data. 144 bits per quadword, 576 total.
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*/
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#define LINE_SIZE 64
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#define LINE_ADDR_MSK (LINE_SIZE - 1)
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#define QW_PER_LINE 4
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#define QW_BYTES (LINE_SIZE / QW_PER_LINE)
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#define QW_BITS 144
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#define LAST_BIT (576 - 1)
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qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
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where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
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where = (LAST_BIT - where_in_line);
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map_index = where >> 2;
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map_offset = where & 0x3;
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map_val = map->dimm_map[map_index];
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map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));
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sprintf(buf, "%s, pin %3d",
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prop->dimm_labels[first_dimm + map_val],
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map->pin_map[where_in_line]);
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} else {
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int dimm;
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/* Multi-bit error, we just dump out all the
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* dimm labels associated with this bank.
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*/
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for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
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sprintf(buf, "%s ",
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prop->dimm_labels[first_dimm + dimm]);
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buf += strlen(buf);
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}
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}
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return 0;
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}
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/* Accessing the registers is slightly complicated. If you want
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* to get at the memory controller which is on the same processor
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* the code is executing, you must use special ASI load/store else
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* you go through the global mapping.
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*/
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static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
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{
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unsigned long ret, this_cpu;
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preempt_disable();
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this_cpu = real_hard_smp_processor_id();
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if (mp->portid == this_cpu) {
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (ret)
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: "r" (offset), "i" (ASI_MCU_CTRL_REG));
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} else {
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (ret)
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: "r" (mp->regs + offset),
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"i" (ASI_PHYS_BYPASS_EC_E));
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}
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preempt_enable();
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return ret;
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}
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#if 0 /* currently unused */
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static void write_mcreg(struct mctrl_info *mp, unsigned long offset, u64 val)
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{
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if (mp->portid == smp_processor_id()) {
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__asm__ __volatile__("stxa %0, [%1] %2"
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: : "r" (val),
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"r" (offset), "i" (ASI_MCU_CTRL_REG));
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} else {
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__asm__ __volatile__("ldxa %0, [%1] %2"
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: : "r" (val),
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"r" (mp->regs + offset),
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"i" (ASI_PHYS_BYPASS_EC_E));
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}
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}
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#endif
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static void interpret_one_decode_reg(struct mctrl_info *mp, int which_bank, u64 val)
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{
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struct bank_info *p = &mp->logical_banks[which_bank];
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p->mp = mp;
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p->bank_id = (CHMCTRL_NBANKS * mp->portid) + which_bank;
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p->raw_reg = val;
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p->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
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p->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
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p->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
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p->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
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p->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
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p->base = (p->um);
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p->base &= ~(p->uk);
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p->base <<= PA_UPPER_BITS_SHIFT;
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switch(p->lk) {
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case 0xf:
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default:
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p->interleave = 1;
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break;
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case 0xe:
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p->interleave = 2;
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break;
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case 0xc:
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p->interleave = 4;
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break;
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case 0x8:
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p->interleave = 8;
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break;
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case 0x0:
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p->interleave = 16;
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break;
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};
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/* UK[10] is reserved, and UK[11] is not set for the SDRAM
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* bank size definition.
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*/
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p->size = (((unsigned long)p->uk &
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((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
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p->size /= p->interleave;
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}
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static void fetch_decode_regs(struct mctrl_info *mp)
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{
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if (mp->layout_size == 0)
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return;
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interpret_one_decode_reg(mp, 0,
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read_mcreg(mp, CHMCTRL_DECODE1));
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interpret_one_decode_reg(mp, 1,
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read_mcreg(mp, CHMCTRL_DECODE2));
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interpret_one_decode_reg(mp, 2,
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read_mcreg(mp, CHMCTRL_DECODE3));
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interpret_one_decode_reg(mp, 3,
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read_mcreg(mp, CHMCTRL_DECODE4));
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}
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static int init_one_mctrl(struct device_node *dp)
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{
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struct mctrl_info *mp = kzalloc(sizeof(*mp), GFP_KERNEL);
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int portid = of_getintprop_default(dp, "portid", -1);
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const struct linux_prom64_registers *regs;
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const void *pval;
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int len;
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if (!mp)
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return -1;
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if (portid == -1)
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goto fail;
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mp->portid = portid;
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pval = of_get_property(dp, "memory-layout", &len);
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mp->layout_size = len;
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if (!pval)
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mp->layout_size = 0;
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else {
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if (mp->layout_size > sizeof(mp->layout_prop))
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goto fail;
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memcpy(&mp->layout_prop, pval, len);
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}
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regs = of_get_property(dp, "reg", NULL);
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if (!regs || regs->reg_size != 0x48)
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goto fail;
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mp->regs = ioremap(regs->phys_addr, regs->reg_size);
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if (mp->regs == NULL)
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goto fail;
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if (mp->layout_size != 0UL) {
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mp->timing_control1 = read_mcreg(mp, CHMCTRL_TCTRL1);
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mp->timing_control2 = read_mcreg(mp, CHMCTRL_TCTRL2);
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mp->timing_control3 = read_mcreg(mp, CHMCTRL_TCTRL3);
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mp->timing_control4 = read_mcreg(mp, CHMCTRL_TCTRL4);
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mp->memaddr_control = read_mcreg(mp, CHMCTRL_MACTRL);
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}
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fetch_decode_regs(mp);
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list_add(&mp->list, &mctrl_list);
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/* Report the device. */
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printk(KERN_INFO "%s: US3 memory controller at %p [%s]\n",
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dp->full_name,
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mp->regs, (mp->layout_size ? "ACTIVE" : "INACTIVE"));
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return 0;
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fail:
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if (mp) {
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if (mp->regs != NULL)
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iounmap(mp->regs);
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kfree(mp);
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}
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return -1;
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}
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static int __init chmc_init(void)
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{
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struct device_node *dp;
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/* This driver is only for cheetah platforms. */
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if (tlb_type != cheetah && tlb_type != cheetah_plus)
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return -ENODEV;
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for_each_node_by_name(dp, "memory-controller")
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init_one_mctrl(dp);
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for_each_node_by_name(dp, "mc-us3")
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init_one_mctrl(dp);
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return 0;
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}
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static void __exit chmc_cleanup(void)
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{
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struct list_head *head = &mctrl_list;
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struct list_head *tmp = head->next;
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for (;;) {
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struct mctrl_info *p =
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list_entry(tmp, struct mctrl_info, list);
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if (tmp == head)
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break;
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tmp = tmp->next;
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list_del(&p->list);
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iounmap(p->regs);
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kfree(p);
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}
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}
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module_init(chmc_init);
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module_exit(chmc_cleanup);
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