551 lines
15 KiB
C
551 lines
15 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "r100d.h"
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#include "r200_reg_safe.h"
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#include "r100_track.h"
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static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
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{
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int vtx_size, i;
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vtx_size = 2;
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if (vtx_fmt_0 & R200_VTX_Z0)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_W0)
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vtx_size++;
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/* blend weight */
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if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
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vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
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if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_N0)
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vtx_size += 3;
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if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_SHININESS_0)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_SHININESS_1)
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vtx_size++;
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for (i = 0; i < 8; i++) {
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int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
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switch (color_size) {
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case 0: break;
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case 1: vtx_size++; break;
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case 2: vtx_size += 3; break;
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case 3: vtx_size += 4; break;
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}
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}
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if (vtx_fmt_0 & R200_VTX_XY1)
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vtx_size += 2;
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if (vtx_fmt_0 & R200_VTX_Z1)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_W1)
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vtx_size++;
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if (vtx_fmt_0 & R200_VTX_N1)
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vtx_size += 3;
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return vtx_size;
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}
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struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
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uint64_t src_offset,
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uint64_t dst_offset,
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unsigned num_gpu_pages,
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struct reservation_object *resv)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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struct radeon_fence *fence;
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uint32_t size;
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uint32_t cur_size;
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int i, num_loops;
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int r = 0;
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/* radeon pitch is /64 */
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size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
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num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
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r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64);
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if (r) {
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DRM_ERROR("radeon: moving bo (%d).\n", r);
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return ERR_PTR(r);
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}
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/* Must wait for 2D idle & clean before DMA or hangs might happen */
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radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
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radeon_ring_write(ring, (1 << 16));
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for (i = 0; i < num_loops; i++) {
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cur_size = size;
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if (cur_size > 0x1FFFFF) {
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cur_size = 0x1FFFFF;
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}
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size -= cur_size;
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radeon_ring_write(ring, PACKET0(0x720, 2));
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radeon_ring_write(ring, src_offset);
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radeon_ring_write(ring, dst_offset);
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radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));
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src_offset += cur_size;
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dst_offset += cur_size;
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}
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radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
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radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
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r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
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if (r) {
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radeon_ring_unlock_undo(rdev, ring);
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return ERR_PTR(r);
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}
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radeon_ring_unlock_commit(rdev, ring, false);
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return fence;
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}
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static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
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{
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int vtx_size, i, tex_size;
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vtx_size = 0;
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for (i = 0; i < 6; i++) {
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tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
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if (tex_size > 4)
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continue;
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vtx_size += tex_size;
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}
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return vtx_size;
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}
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int r200_packet0_check(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
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unsigned idx, unsigned reg)
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{
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struct radeon_bo_list *reloc;
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struct r100_cs_track *track;
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volatile uint32_t *ib;
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uint32_t tmp;
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int r;
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int i;
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int face;
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u32 tile_flags = 0;
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u32 idx_value;
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ib = p->ib.ptr;
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track = (struct r100_cs_track *)p->track;
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idx_value = radeon_get_ib_value(p, idx);
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switch (reg) {
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case RADEON_CRTC_GUI_TRIG_VLINE:
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r = r100_cs_packet_parse_vline(p);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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break;
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/* FIXME: only allow PACKET3 blit? easier to check for out of
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* range access */
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case RADEON_DST_PITCH_OFFSET:
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case RADEON_SRC_PITCH_OFFSET:
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r = r100_reloc_pitch_offset(p, pkt, idx, reg);
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if (r)
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return r;
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break;
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case RADEON_RB3D_DEPTHOFFSET:
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->zb.robj = reloc->robj;
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track->zb.offset = idx_value;
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track->zb_dirty = true;
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ib[idx] = idx_value + ((u32)reloc->gpu_offset);
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break;
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case RADEON_RB3D_COLOROFFSET:
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->cb[0].robj = reloc->robj;
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track->cb[0].offset = idx_value;
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track->cb_dirty = true;
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ib[idx] = idx_value + ((u32)reloc->gpu_offset);
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break;
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case R200_PP_TXOFFSET_0:
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case R200_PP_TXOFFSET_1:
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case R200_PP_TXOFFSET_2:
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case R200_PP_TXOFFSET_3:
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case R200_PP_TXOFFSET_4:
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case R200_PP_TXOFFSET_5:
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i = (reg - R200_PP_TXOFFSET_0) / 24;
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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if (reloc->tiling_flags & RADEON_TILING_MACRO)
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tile_flags |= R200_TXO_MACRO_TILE;
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if (reloc->tiling_flags & RADEON_TILING_MICRO)
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tile_flags |= R200_TXO_MICRO_TILE;
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tmp = idx_value & ~(0x7 << 2);
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tmp |= tile_flags;
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ib[idx] = tmp + ((u32)reloc->gpu_offset);
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} else
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ib[idx] = idx_value + ((u32)reloc->gpu_offset);
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track->textures[i].robj = reloc->robj;
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track->tex_dirty = true;
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break;
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case R200_PP_CUBIC_OFFSET_F1_0:
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case R200_PP_CUBIC_OFFSET_F2_0:
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case R200_PP_CUBIC_OFFSET_F3_0:
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case R200_PP_CUBIC_OFFSET_F4_0:
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case R200_PP_CUBIC_OFFSET_F5_0:
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case R200_PP_CUBIC_OFFSET_F1_1:
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case R200_PP_CUBIC_OFFSET_F2_1:
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case R200_PP_CUBIC_OFFSET_F3_1:
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case R200_PP_CUBIC_OFFSET_F4_1:
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case R200_PP_CUBIC_OFFSET_F5_1:
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case R200_PP_CUBIC_OFFSET_F1_2:
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case R200_PP_CUBIC_OFFSET_F2_2:
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case R200_PP_CUBIC_OFFSET_F3_2:
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case R200_PP_CUBIC_OFFSET_F4_2:
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case R200_PP_CUBIC_OFFSET_F5_2:
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case R200_PP_CUBIC_OFFSET_F1_3:
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case R200_PP_CUBIC_OFFSET_F2_3:
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case R200_PP_CUBIC_OFFSET_F3_3:
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case R200_PP_CUBIC_OFFSET_F4_3:
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case R200_PP_CUBIC_OFFSET_F5_3:
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case R200_PP_CUBIC_OFFSET_F1_4:
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case R200_PP_CUBIC_OFFSET_F2_4:
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case R200_PP_CUBIC_OFFSET_F3_4:
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case R200_PP_CUBIC_OFFSET_F4_4:
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case R200_PP_CUBIC_OFFSET_F5_4:
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case R200_PP_CUBIC_OFFSET_F1_5:
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case R200_PP_CUBIC_OFFSET_F2_5:
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case R200_PP_CUBIC_OFFSET_F3_5:
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case R200_PP_CUBIC_OFFSET_F4_5:
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case R200_PP_CUBIC_OFFSET_F5_5:
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i = (reg - R200_PP_TXOFFSET_0) / 24;
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face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->textures[i].cube_info[face - 1].offset = idx_value;
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ib[idx] = idx_value + ((u32)reloc->gpu_offset);
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track->textures[i].cube_info[face - 1].robj = reloc->robj;
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track->tex_dirty = true;
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break;
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case RADEON_RE_WIDTH_HEIGHT:
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track->maxy = ((idx_value >> 16) & 0x7FF);
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track->cb_dirty = true;
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track->zb_dirty = true;
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break;
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case RADEON_RB3D_COLORPITCH:
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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if (reloc->tiling_flags & RADEON_TILING_MACRO)
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tile_flags |= RADEON_COLOR_TILE_ENABLE;
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if (reloc->tiling_flags & RADEON_TILING_MICRO)
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tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
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tmp = idx_value & ~(0x7 << 16);
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tmp |= tile_flags;
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ib[idx] = tmp;
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} else
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ib[idx] = idx_value;
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track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
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track->cb_dirty = true;
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break;
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case RADEON_RB3D_DEPTHPITCH:
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track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
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track->zb_dirty = true;
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break;
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case RADEON_RB3D_CNTL:
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switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
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case 7:
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case 8:
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case 9:
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case 11:
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case 12:
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track->cb[0].cpp = 1;
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break;
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case 3:
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case 4:
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case 15:
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track->cb[0].cpp = 2;
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break;
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case 6:
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track->cb[0].cpp = 4;
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break;
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default:
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DRM_ERROR("Invalid color buffer format (%d) !\n",
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((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
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return -EINVAL;
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}
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if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
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DRM_ERROR("No support for depth xy offset in kms\n");
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return -EINVAL;
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}
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track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
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track->cb_dirty = true;
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track->zb_dirty = true;
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break;
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case RADEON_RB3D_ZSTENCILCNTL:
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switch (idx_value & 0xf) {
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case 0:
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track->zb.cpp = 2;
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break;
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case 2:
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case 3:
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case 4:
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case 5:
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case 9:
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case 11:
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track->zb.cpp = 4;
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break;
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default:
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break;
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}
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track->zb_dirty = true;
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break;
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case RADEON_RB3D_ZPASS_ADDR:
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r = radeon_cs_packet_next_reloc(p, &reloc, 0);
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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radeon_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx] = idx_value + ((u32)reloc->gpu_offset);
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break;
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case RADEON_PP_CNTL:
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{
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uint32_t temp = idx_value >> 4;
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for (i = 0; i < track->num_texture; i++)
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track->textures[i].enabled = !!(temp & (1 << i));
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track->tex_dirty = true;
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}
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break;
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case RADEON_SE_VF_CNTL:
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track->vap_vf_cntl = idx_value;
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break;
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case 0x210c:
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/* VAP_VF_MAX_VTX_INDX */
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track->max_indx = idx_value & 0x00FFFFFFUL;
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break;
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case R200_SE_VTX_FMT_0:
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track->vtx_size = r200_get_vtx_size_0(idx_value);
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break;
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case R200_SE_VTX_FMT_1:
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track->vtx_size += r200_get_vtx_size_1(idx_value);
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break;
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case R200_PP_TXSIZE_0:
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case R200_PP_TXSIZE_1:
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case R200_PP_TXSIZE_2:
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case R200_PP_TXSIZE_3:
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case R200_PP_TXSIZE_4:
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case R200_PP_TXSIZE_5:
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i = (reg - R200_PP_TXSIZE_0) / 32;
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track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
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track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
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track->tex_dirty = true;
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break;
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case R200_PP_TXPITCH_0:
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case R200_PP_TXPITCH_1:
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case R200_PP_TXPITCH_2:
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case R200_PP_TXPITCH_3:
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case R200_PP_TXPITCH_4:
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case R200_PP_TXPITCH_5:
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i = (reg - R200_PP_TXPITCH_0) / 32;
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track->textures[i].pitch = idx_value + 32;
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track->tex_dirty = true;
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break;
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case R200_PP_TXFILTER_0:
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case R200_PP_TXFILTER_1:
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case R200_PP_TXFILTER_2:
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case R200_PP_TXFILTER_3:
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case R200_PP_TXFILTER_4:
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case R200_PP_TXFILTER_5:
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i = (reg - R200_PP_TXFILTER_0) / 32;
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track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
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>> R200_MAX_MIP_LEVEL_SHIFT);
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tmp = (idx_value >> 23) & 0x7;
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if (tmp == 2 || tmp == 6)
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track->textures[i].roundup_w = false;
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tmp = (idx_value >> 27) & 0x7;
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if (tmp == 2 || tmp == 6)
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track->textures[i].roundup_h = false;
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track->tex_dirty = true;
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break;
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case R200_PP_TXMULTI_CTL_0:
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case R200_PP_TXMULTI_CTL_1:
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case R200_PP_TXMULTI_CTL_2:
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case R200_PP_TXMULTI_CTL_3:
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case R200_PP_TXMULTI_CTL_4:
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case R200_PP_TXMULTI_CTL_5:
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i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
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break;
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case R200_PP_TXFORMAT_X_0:
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case R200_PP_TXFORMAT_X_1:
|
|
case R200_PP_TXFORMAT_X_2:
|
|
case R200_PP_TXFORMAT_X_3:
|
|
case R200_PP_TXFORMAT_X_4:
|
|
case R200_PP_TXFORMAT_X_5:
|
|
i = (reg - R200_PP_TXFORMAT_X_0) / 32;
|
|
track->textures[i].txdepth = idx_value & 0x7;
|
|
tmp = (idx_value >> 16) & 0x3;
|
|
/* 2D, 3D, CUBE */
|
|
switch (tmp) {
|
|
case 0:
|
|
case 3:
|
|
case 4:
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
/* 1D/2D */
|
|
track->textures[i].tex_coord_type = 0;
|
|
break;
|
|
case 1:
|
|
/* CUBE */
|
|
track->textures[i].tex_coord_type = 2;
|
|
break;
|
|
case 2:
|
|
/* 3D */
|
|
track->textures[i].tex_coord_type = 1;
|
|
break;
|
|
}
|
|
track->tex_dirty = true;
|
|
break;
|
|
case R200_PP_TXFORMAT_0:
|
|
case R200_PP_TXFORMAT_1:
|
|
case R200_PP_TXFORMAT_2:
|
|
case R200_PP_TXFORMAT_3:
|
|
case R200_PP_TXFORMAT_4:
|
|
case R200_PP_TXFORMAT_5:
|
|
i = (reg - R200_PP_TXFORMAT_0) / 32;
|
|
if (idx_value & R200_TXFORMAT_NON_POWER2) {
|
|
track->textures[i].use_pitch = 1;
|
|
} else {
|
|
track->textures[i].use_pitch = 0;
|
|
track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
|
|
track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
|
|
}
|
|
if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
|
|
track->textures[i].lookup_disable = true;
|
|
switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
|
|
case R200_TXFORMAT_I8:
|
|
case R200_TXFORMAT_RGB332:
|
|
case R200_TXFORMAT_Y8:
|
|
track->textures[i].cpp = 1;
|
|
track->textures[i].compress_format = R100_TRACK_COMP_NONE;
|
|
break;
|
|
case R200_TXFORMAT_AI88:
|
|
case R200_TXFORMAT_ARGB1555:
|
|
case R200_TXFORMAT_RGB565:
|
|
case R200_TXFORMAT_ARGB4444:
|
|
case R200_TXFORMAT_VYUY422:
|
|
case R200_TXFORMAT_YVYU422:
|
|
case R200_TXFORMAT_LDVDU655:
|
|
case R200_TXFORMAT_DVDU88:
|
|
case R200_TXFORMAT_AVYU4444:
|
|
track->textures[i].cpp = 2;
|
|
track->textures[i].compress_format = R100_TRACK_COMP_NONE;
|
|
break;
|
|
case R200_TXFORMAT_ARGB8888:
|
|
case R200_TXFORMAT_RGBA8888:
|
|
case R200_TXFORMAT_ABGR8888:
|
|
case R200_TXFORMAT_BGR111110:
|
|
case R200_TXFORMAT_LDVDU8888:
|
|
track->textures[i].cpp = 4;
|
|
track->textures[i].compress_format = R100_TRACK_COMP_NONE;
|
|
break;
|
|
case R200_TXFORMAT_DXT1:
|
|
track->textures[i].cpp = 1;
|
|
track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
|
|
break;
|
|
case R200_TXFORMAT_DXT23:
|
|
case R200_TXFORMAT_DXT45:
|
|
track->textures[i].cpp = 1;
|
|
track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
|
|
break;
|
|
}
|
|
track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
|
|
track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
|
|
track->tex_dirty = true;
|
|
break;
|
|
case R200_PP_CUBIC_FACES_0:
|
|
case R200_PP_CUBIC_FACES_1:
|
|
case R200_PP_CUBIC_FACES_2:
|
|
case R200_PP_CUBIC_FACES_3:
|
|
case R200_PP_CUBIC_FACES_4:
|
|
case R200_PP_CUBIC_FACES_5:
|
|
tmp = idx_value;
|
|
i = (reg - R200_PP_CUBIC_FACES_0) / 32;
|
|
for (face = 0; face < 4; face++) {
|
|
track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
|
|
track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
|
|
}
|
|
track->tex_dirty = true;
|
|
break;
|
|
default:
|
|
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void r200_set_safe_registers(struct radeon_device *rdev)
|
|
{
|
|
rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
|
|
rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
|
|
}
|