436 lines
12 KiB
C
436 lines
12 KiB
C
/*
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* EHCI HCD (Host Controller Driver) PCI Bus Glue.
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*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include "ehci.h"
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#include "pci-quirks.h"
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#define DRIVER_DESC "EHCI PCI platform driver"
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static const char hcd_name[] = "ehci-pci";
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/* defined here to avoid adding to pci_ids.h for single instance use */
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#define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
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/*-------------------------------------------------------------------------*/
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
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static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
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{
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return pdev->vendor == PCI_VENDOR_ID_INTEL &&
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pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
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}
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/*
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* This is the list of PCI IDs for the devices that have EHCI USB class and
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* specific drivers for that. One of the example is a ChipIdea device installed
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* on some Intel MID platforms.
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*/
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static const struct pci_device_id bypass_pci_id_table[] = {
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/* ChipIdea on Intel MID platform */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
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{}
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};
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static inline bool is_bypassed_id(struct pci_dev *pdev)
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{
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return !!pci_match_id(bypass_pci_id_table, pdev);
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}
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/*
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* 0x84 is the offset of in/out threshold register,
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* and it is the same offset as the register of 'hostpc'.
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*/
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#define intel_quark_x1000_insnreg01 hostpc
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/* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
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#define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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{
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int retval;
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/* we expect static quirk code to handle the "extended capabilities"
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* (currently just BIOS handoff) allowed starting with EHCI 0.96
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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retval = pci_set_mwi(pdev);
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if (!retval)
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ehci_dbg(ehci, "MWI active\n");
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/* Reset the threshold limit */
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if (is_intel_quark_x1000(pdev)) {
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/*
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* For the Intel QUARK X1000, raise the I/O threshold to the
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* maximum usable value in order to improve performance.
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*/
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ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
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ehci->regs->intel_quark_x1000_insnreg01);
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}
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return 0;
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}
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/* called during probe() after chip reset completes */
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static int ehci_pci_setup(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u32 temp;
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int retval;
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ehci->caps = hcd->regs;
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/*
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* ehci_init() causes memory for DMA transfers to be
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* allocated. Thus, any vendor-specific workarounds based on
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* limiting the type of memory used for DMA transfers must
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* happen before ehci_setup() is called.
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*
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* Most other workarounds can be done either before or after
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* init and reset; they are located here too.
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*/
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TOSHIBA_2:
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/* celleb's companion chip */
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if (pdev->device == 0x01b5) {
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
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ehci->big_endian_mmio = 1;
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#else
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ehci_warn(ehci,
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"unsupported big endian Toshiba quirk\n");
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#endif
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_BIT_MASK(31)) < 0)
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ehci_warn(ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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/* Some NForce2 chips have problems with selective suspend;
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* fixed in newer silicon.
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*/
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case 0x0068:
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if (pdev->revision < 0xa4)
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ehci->no_selective_suspend = 1;
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break;
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}
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break;
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case PCI_VENDOR_ID_INTEL:
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if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
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hcd->has_tt = 1;
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break;
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
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hcd->has_tt = 1;
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD PLL quirk */
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if (usb_amd_find_chipset_info())
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ehci->amd_pll_fix = 1;
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info(ehci, "ignoring AMD8111 (errata)\n");
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retval = -EIO;
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goto done;
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}
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/*
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* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
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* read/write memory space which does not belong to it when
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* there is NULL pointer with T-bit set to 1 in the frame list
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* table. To avoid the issue, the frame list link pointer
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* should always contain a valid pointer to a inactive qh.
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*/
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if (pdev->device == 0x7808) {
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ehci->use_dummy_qh = 1;
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ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
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}
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break;
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case PCI_VENDOR_ID_VIA:
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if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
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u8 tmp;
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/* The VT6212 defaults to a 1 usec EHCI sleep time which
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* hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
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* that sleep time use the conventional 10 usec.
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*/
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pci_read_config_byte(pdev, 0x4b, &tmp);
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if (tmp & 0x20)
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break;
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pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
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}
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break;
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case PCI_VENDOR_ID_ATI:
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/* AMD PLL quirk */
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if (usb_amd_find_chipset_info())
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ehci->amd_pll_fix = 1;
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/*
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* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
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* read/write memory space which does not belong to it when
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* there is NULL pointer with T-bit set to 1 in the frame list
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* table. To avoid the issue, the frame list link pointer
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* should always contain a valid pointer to a inactive qh.
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*/
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if (pdev->device == 0x4396) {
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ehci->use_dummy_qh = 1;
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ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
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}
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/* SB600 and old version of SB700 have a bug in EHCI controller,
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* which causes usb devices lose response in some cases.
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*/
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if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
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usb_amd_hang_symptom_quirk()) {
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u8 tmp;
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ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
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pci_read_config_byte(pdev, 0x53, &tmp);
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pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
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}
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break;
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case PCI_VENDOR_ID_NETMOS:
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/* MosChip frame-index-register bug */
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ehci_info(ehci, "applying MosChip frame-index workaround\n");
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ehci->frame_index_bug = 1;
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break;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if (((temp >> 13) & 7) == 1) {
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u32 hcs_params = ehci_readl(ehci,
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&ehci->caps->hcs_params);
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temp &= 0x1fff;
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ehci->debug = hcd->regs + temp;
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temp = ehci_readl(ehci, &ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(hcs_params),
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(temp & DBGP_ENABLED) ? " IN USE" : "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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retval = ehci_setup(hcd);
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if (retval)
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return retval;
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/* These workarounds need to be applied after ehci_setup() */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_NEC:
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ehci->need_io_watchdog = 0;
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break;
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case PCI_VENDOR_ID_INTEL:
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ehci->need_io_watchdog = 0;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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switch (pdev->device) {
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/* MCP89 chips on the MacBookAir3,1 give EPROTO when
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* fetching device descriptors unless LPM is disabled.
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* There are also intermittent problems enumerating
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* devices with PPCD enabled.
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*/
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case 0x0d9d:
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ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
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ehci->has_ppcd = 0;
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ehci->command &= ~CMD_PPCEE;
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break;
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}
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break;
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}
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
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ehci_dbg(ehci, "bogus port configuration: "
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"cc=%d x pcc=%d < ports=%d\n",
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HCS_N_CC(ehci->hcs_params),
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HCS_N_PCC(ehci->hcs_params),
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HCS_N_PORTS(ehci->hcs_params));
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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}
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/* Serial Bus Release Number is at PCI 0x60 offset */
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if (pdev->vendor == PCI_VENDOR_ID_STMICRO
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&& pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
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; /* ConneXT has no sbrn register */
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else
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* Keep this around for a while just in case some EHCI
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* implementation uses legacy PCI PM support. This test
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* can be removed on 17 Dec 2009 if the dev_warn() hasn't
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* been triggered by then.
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*/
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if (!device_can_wakeup(&pdev->dev)) {
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u16 port_wake;
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pci_read_config_word(pdev, 0x62, &port_wake);
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if (port_wake & 0x0001) {
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dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
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device_set_wakeup_capable(&pdev->dev, 1);
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}
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}
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#ifdef CONFIG_PM
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if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
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ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
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#endif
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retval = ehci_pci_reinit(ehci, pdev);
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done:
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return retval;
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}
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_PM
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/* suspend/resume, section 4.3 */
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/* These routines rely on the PCI bus glue
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* to handle powerdown and wakeup, and currently also on
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* transceivers that don't need any software attention to set up
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* the right sort of wakeup.
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* Also they depend on separate root hub suspend/resume.
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*/
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static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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if (ehci_resume(hcd, hibernated) != 0)
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(void) ehci_pci_reinit(ehci, pdev);
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return 0;
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}
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#else
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#define ehci_suspend NULL
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#define ehci_pci_resume NULL
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#endif /* CONFIG_PM */
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static struct hc_driver __read_mostly ehci_pci_hc_driver;
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static const struct ehci_driver_overrides pci_overrides __initconst = {
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.reset = ehci_pci_setup,
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};
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/*-------------------------------------------------------------------------*/
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static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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if (is_bypassed_id(pdev))
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return -ENODEV;
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return usb_hcd_pci_probe(pdev, id);
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}
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids [] = { {
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/* handle any USB 2.0 EHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
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.driver_data = (unsigned long) &ehci_pci_hc_driver,
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}, {
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PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
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.driver_data = (unsigned long) &ehci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ehci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = ehci_pci_probe,
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.remove = usb_hcd_pci_remove,
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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static int __init ehci_pci_init(void)
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{
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if (usb_disabled())
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return -ENODEV;
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pr_info("%s: " DRIVER_DESC "\n", hcd_name);
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ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
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/* Entries for the PCI suspend/resume callbacks are special */
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ehci_pci_hc_driver.pci_suspend = ehci_suspend;
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ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
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return pci_register_driver(&ehci_pci_driver);
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}
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module_init(ehci_pci_init);
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static void __exit ehci_pci_cleanup(void)
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{
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pci_unregister_driver(&ehci_pci_driver);
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}
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module_exit(ehci_pci_cleanup);
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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_AUTHOR("David Brownell");
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MODULE_AUTHOR("Alan Stern");
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MODULE_LICENSE("GPL");
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