185 lines
4.7 KiB
C
185 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* arch/powerpc/sysdev/qe_lib/qe_io.c
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*
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* QE Parallel I/O ports configuration routines
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*
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* Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <LeoLi@freescale.com>
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* Based on code from Shlomi Gridish <gridish@freescale.com>
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/qe.h>
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#undef DEBUG
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static struct qe_pio_regs __iomem *par_io;
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static int num_par_io_ports = 0;
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int par_io_init(struct device_node *np)
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{
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struct resource res;
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int ret;
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u32 num_ports;
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/* Map Parallel I/O ports registers */
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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return ret;
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par_io = ioremap(res.start, resource_size(&res));
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if (!of_property_read_u32(np, "num-ports", &num_ports))
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num_par_io_ports = num_ports;
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return 0;
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}
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void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
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int open_drain, int assignment, int has_irq)
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{
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u32 pin_mask1bit;
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u32 pin_mask2bits;
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u32 new_mask2bits;
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u32 tmp_val;
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/* calculate pin location for single and 2 bits information */
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pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
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/* Set open drain, if required */
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tmp_val = qe_ioread32be(&par_io->cpodr);
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if (open_drain)
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qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
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else
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qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
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/* define direction */
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tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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qe_ioread32be(&par_io->cpdir2) :
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qe_ioread32be(&par_io->cpdir1);
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/* get all bits mask for 2 bit per port */
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pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
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(pin % (QE_PIO_PINS / 2) + 1) * 2));
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/* Get the final mask we need for the right definition */
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new_mask2bits = (u32) (dir << (QE_PIO_PINS -
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(pin % (QE_PIO_PINS / 2) + 1) * 2));
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/* clear and set 2 bits mask */
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if (pin > (QE_PIO_PINS / 2) - 1) {
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qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
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tmp_val &= ~pin_mask2bits;
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qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
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} else {
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qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
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tmp_val &= ~pin_mask2bits;
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qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
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}
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/* define pin assignment */
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tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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qe_ioread32be(&par_io->cppar2) :
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qe_ioread32be(&par_io->cppar1);
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new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
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(pin % (QE_PIO_PINS / 2) + 1) * 2));
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/* clear and set 2 bits mask */
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if (pin > (QE_PIO_PINS / 2) - 1) {
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qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
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tmp_val &= ~pin_mask2bits;
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qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
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} else {
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qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
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tmp_val &= ~pin_mask2bits;
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qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
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}
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}
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EXPORT_SYMBOL(__par_io_config_pin);
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int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
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int assignment, int has_irq)
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{
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if (!par_io || port >= num_par_io_ports)
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return -EINVAL;
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__par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment,
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has_irq);
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return 0;
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}
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EXPORT_SYMBOL(par_io_config_pin);
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int par_io_data_set(u8 port, u8 pin, u8 val)
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{
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u32 pin_mask, tmp_val;
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if (port >= num_par_io_ports)
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return -EINVAL;
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if (pin >= QE_PIO_PINS)
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return -EINVAL;
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/* calculate pin location */
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pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
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tmp_val = qe_ioread32be(&par_io[port].cpdata);
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if (val == 0) /* clear */
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qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
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else /* set */
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qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
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return 0;
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}
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EXPORT_SYMBOL(par_io_data_set);
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int par_io_of_config(struct device_node *np)
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{
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struct device_node *pio;
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int pio_map_len;
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const __be32 *pio_map;
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if (par_io == NULL) {
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printk(KERN_ERR "par_io not initialized\n");
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return -1;
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}
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pio = of_parse_phandle(np, "pio-handle", 0);
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if (pio == NULL) {
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printk(KERN_ERR "pio-handle not available\n");
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return -1;
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}
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pio_map = of_get_property(pio, "pio-map", &pio_map_len);
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if (pio_map == NULL) {
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printk(KERN_ERR "pio-map is not set!\n");
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return -1;
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}
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pio_map_len /= sizeof(unsigned int);
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if ((pio_map_len % 6) != 0) {
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printk(KERN_ERR "pio-map format wrong!\n");
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return -1;
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}
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while (pio_map_len > 0) {
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u8 port = be32_to_cpu(pio_map[0]);
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u8 pin = be32_to_cpu(pio_map[1]);
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int dir = be32_to_cpu(pio_map[2]);
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int open_drain = be32_to_cpu(pio_map[3]);
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int assignment = be32_to_cpu(pio_map[4]);
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int has_irq = be32_to_cpu(pio_map[5]);
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par_io_config_pin(port, pin, dir, open_drain,
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assignment, has_irq);
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pio_map += 6;
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pio_map_len -= 6;
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}
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of_node_put(pio);
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return 0;
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}
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EXPORT_SYMBOL(par_io_of_config);
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