a8e326a911
Allow the the driver to change the clock supplied from the CAR directly, minimizing the need to divide the clock inside the SDMMC module itself. This allows for higher clock speeds than the default 48MHz supplied to the module and is a prerequisite to support DDR signaling modes, where the Tegra host needs to be run with a fixed internal divider of 2 for data to be sampled correctly. (Tegra K1 TRM v03p chapter 29.7.1.1) Also enable the broken preset value quirk as the preset values need to be adapted to the changed clocking. While Tegra114+ allows this through vendor registers, there is no such way for Tegra30. Takes the easy way out and keep things consistent between the different SoC generations by flagging the preset registers as unusable. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
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| card | ||
| core | ||
| host | ||
| Kconfig | ||
| Makefile | ||