236 lines
6.6 KiB
C
236 lines
6.6 KiB
C
/*
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* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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*/
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#ifndef __PPC_SYSTEM_H
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#define __PPC_SYSTEM_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <asm/atomic.h>
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#include <asm/hw_irq.h>
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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* read_barrier_depends() prevents data-dependent loads being reordered
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* across this point (nop on PPC).
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*
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* We can use the eieio instruction for wmb, but since it doesn't
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* give any ordering guarantees about loads, we have to use the
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* stronger but slower sync instruction for mb and rmb.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif /* CONFIG_SMP */
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#ifdef __KERNEL__
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struct task_struct;
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struct pt_regs;
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extern void print_backtrace(unsigned long *);
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extern void show_regs(struct pt_regs * regs);
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extern void flush_instruction_cache(void);
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extern void hard_reset_now(void);
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extern void poweroff_now(void);
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#ifdef CONFIG_6xx
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extern long _get_L2CR(void);
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extern long _get_L3CR(void);
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extern void _set_L2CR(unsigned long);
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extern void _set_L3CR(unsigned long);
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#else
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#define _get_L2CR() 0L
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#define _get_L3CR() 0L
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#define _set_L2CR(val) do { } while(0)
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#define _set_L3CR(val) do { } while(0)
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#endif
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extern void via_cuda_init(void);
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extern void pmac_nvram_init(void);
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extern void chrp_nvram_init(void);
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extern void read_rtc_time(void);
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extern void pmac_find_display(void);
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extern void giveup_fpu(struct task_struct *);
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extern void enable_kernel_fp(void);
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extern void flush_fp_to_thread(struct task_struct *);
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extern void enable_kernel_altivec(void);
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extern void giveup_altivec(struct task_struct *);
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extern void load_up_altivec(struct task_struct *);
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extern int emulate_altivec(struct pt_regs *);
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extern void giveup_spe(struct task_struct *);
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extern void load_up_spe(struct task_struct *);
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extern int fix_alignment(struct pt_regs *);
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extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
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extern void cvt_df(double *from, float *to, struct thread_struct *thread);
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#ifdef CONFIG_ALTIVEC
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extern void flush_altivec_to_thread(struct task_struct *);
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#else
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static inline void flush_altivec_to_thread(struct task_struct *t)
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{
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}
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#endif
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#ifdef CONFIG_SPE
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extern void flush_spe_to_thread(struct task_struct *);
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#else
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static inline void flush_spe_to_thread(struct task_struct *t)
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{
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}
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#endif
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extern int call_rtas(const char *, int, int, unsigned long *, ...);
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extern void cacheable_memzero(void *p, unsigned int nb);
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extern void *cacheable_memcpy(void *, const void *, unsigned int);
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extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
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extern void bad_page_fault(struct pt_regs *, unsigned long, int);
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extern int die(const char *, struct pt_regs *, long);
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extern void _exception(int, struct pt_regs *, int, unsigned long);
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void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
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#ifdef CONFIG_BOOKE_WDT
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extern u32 booke_wdt_enabled;
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extern u32 booke_wdt_period;
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#endif /* CONFIG_BOOKE_WDT */
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struct device_node;
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extern void note_scsi_host(struct device_node *, void *);
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extern struct task_struct *__switch_to(struct task_struct *,
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struct task_struct *);
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#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
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struct thread_struct;
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extern struct task_struct *_switch(struct thread_struct *prev,
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struct thread_struct *next);
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extern unsigned int rtas_data;
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static __inline__ unsigned long
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xchg_u32(volatile void *p, unsigned long val)
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{
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unsigned long prev;
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__asm__ __volatile__ ("\n\
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1: lwarx %0,0,%2 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %3,0,%2 \n\
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bne- 1b"
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: "=&r" (prev), "=m" (*(volatile unsigned long *)p)
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: "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
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: "cc", "memory");
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return prev;
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}
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/*
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* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid xchg().
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*/
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extern void __xchg_called_with_bad_pointer(void);
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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switch (size) {
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case 4:
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return (unsigned long) xchg_u32(ptr, x);
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#if 0 /* xchg_u64 doesn't exist on 32-bit PPC */
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case 8:
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return (unsigned long) xchg_u64(ptr, x);
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#endif /* 0 */
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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extern inline void * xchg_ptr(void * m, void * val)
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{
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return (void *) xchg_u32(m, (unsigned long) val);
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}
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
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{
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unsigned int prev;
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__asm__ __volatile__ ("\n\
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1: lwarx %0,0,%2 \n\
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cmpw 0,%0,%3 \n\
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bne 2f \n"
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PPC405_ERR77(0,%2)
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" stwcx. %4,0,%2 \n\
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bne- 1b\n"
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#ifdef CONFIG_SMP
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" sync\n"
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#endif /* CONFIG_SMP */
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"2:"
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: "=&r" (prev), "=m" (*p)
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: "r" (p), "r" (old), "r" (new), "m" (*p)
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: "cc", "memory");
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return prev;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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#if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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#endif /* 0 */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif /* __PPC_SYSTEM_H */
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