303 lines
6.7 KiB
ArmAsm
303 lines
6.7 KiB
ArmAsm
/*
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* arch/xtensa/kernel/coprocessor.S
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*
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* Xtensa processor configuration-specific table of coprocessor and
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* other custom register layout information.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 - 2007 Tensilica Inc.
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/coprocessor.h>
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#include <asm/current.h>
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#include <asm/regs.h>
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/*
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* Rules for coprocessor state manipulation on SMP:
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*
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* - a task may have live coprocessors only on one CPU.
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*
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* - whether coprocessor context of task T is live on some CPU is
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* denoted by T's thread_info->cpenable.
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*
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* - non-zero thread_info->cpenable means that thread_info->cp_owner_cpu
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* is valid in the T's thread_info. Zero thread_info->cpenable means that
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* coprocessor context is valid in the T's thread_info.
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*
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* - if a coprocessor context of task T is live on CPU X, only CPU X changes
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* T's thread_info->cpenable, cp_owner_cpu and coprocessor save area.
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* This is done by making sure that for the task T with live coprocessor
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* on CPU X cpenable SR is 0 when T runs on any other CPU Y.
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* When fast_coprocessor exception is taken on CPU Y it goes to the
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* C-level do_coprocessor that uses IPI to make CPU X flush T's coprocessors.
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*/
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#if XTENSA_HAVE_COPROCESSORS
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/*
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* Macros for lazy context switch.
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*/
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#define SAVE_CP_REGS(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.align 4; \
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.Lsave_cp_regs_cp##x: \
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xchal_cp##x##_store a2 a3 a4 a5 a6; \
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ret; \
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.endif
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#define LOAD_CP_REGS(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.align 4; \
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.Lload_cp_regs_cp##x: \
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xchal_cp##x##_load a2 a3 a4 a5 a6; \
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ret; \
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.endif
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#define CP_REGS_TAB(x) \
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.if XTENSA_HAVE_COPROCESSOR(x); \
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.long .Lsave_cp_regs_cp##x; \
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.long .Lload_cp_regs_cp##x; \
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.else; \
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.long 0, 0; \
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.endif; \
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.long THREAD_XTREGS_CP##x
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#define CP_REGS_TAB_SAVE 0
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#define CP_REGS_TAB_LOAD 4
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#define CP_REGS_TAB_OFFSET 8
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__XTENSA_HANDLER
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SAVE_CP_REGS(0)
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SAVE_CP_REGS(1)
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SAVE_CP_REGS(2)
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SAVE_CP_REGS(3)
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SAVE_CP_REGS(4)
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SAVE_CP_REGS(5)
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SAVE_CP_REGS(6)
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SAVE_CP_REGS(7)
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LOAD_CP_REGS(0)
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LOAD_CP_REGS(1)
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LOAD_CP_REGS(2)
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LOAD_CP_REGS(3)
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LOAD_CP_REGS(4)
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LOAD_CP_REGS(5)
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LOAD_CP_REGS(6)
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LOAD_CP_REGS(7)
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.align 4
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.Lcp_regs_jump_table:
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CP_REGS_TAB(0)
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CP_REGS_TAB(1)
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CP_REGS_TAB(2)
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CP_REGS_TAB(3)
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CP_REGS_TAB(4)
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CP_REGS_TAB(5)
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CP_REGS_TAB(6)
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CP_REGS_TAB(7)
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/*
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* Entry condition:
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*
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* a0: trashed, original value saved on stack (PT_AREG0)
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* a1: a1
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* a2: new stack pointer, original in DEPC
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* a3: a3
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* depc: a2, original value saved on stack (PT_DEPC)
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* excsave_1: dispatch table
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*
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* PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
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* < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
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*/
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ENTRY(fast_coprocessor)
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s32i a3, a2, PT_AREG3
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#ifdef CONFIG_SMP
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/*
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* Check if any coprocessor context is live on another CPU
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* and if so go through the C-level coprocessor exception handler
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* to flush it to memory.
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*/
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GET_THREAD_INFO (a0, a2)
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l32i a3, a0, THREAD_CPENABLE
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beqz a3, .Lload_local
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/*
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* Pairs with smp_wmb in local_coprocessor_release_all
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* and with both memws below.
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*/
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memw
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l32i a3, a0, THREAD_CPU
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l32i a0, a0, THREAD_CP_OWNER_CPU
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beq a0, a3, .Lload_local
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rsr a0, ps
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l32i a3, a2, PT_AREG3
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bbci.l a0, PS_UM_BIT, 1f
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call0 user_exception
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1: call0 kernel_exception
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#endif
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/* Save remaining registers a1-a3 and SAR */
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.Lload_local:
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rsr a3, sar
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s32i a1, a2, PT_AREG1
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s32i a3, a2, PT_SAR
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mov a1, a2
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rsr a2, depc
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s32i a2, a1, PT_AREG2
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/* The hal macros require up to 4 temporary registers. We use a3..a6. */
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s32i a4, a1, PT_AREG4
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s32i a5, a1, PT_AREG5
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s32i a6, a1, PT_AREG6
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s32i a7, a1, PT_AREG7
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s32i a8, a1, PT_AREG8
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s32i a9, a1, PT_AREG9
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s32i a10, a1, PT_AREG10
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/* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
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rsr a3, exccause
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addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
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/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
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ssl a3 # SAR: 32 - coprocessor_number
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movi a2, 1
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rsr a0, cpenable
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sll a2, a2
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or a0, a0, a2
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wsr a0, cpenable
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rsync
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/* Get coprocessor save/load table entry (a7). */
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movi a7, .Lcp_regs_jump_table
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addx8 a7, a3, a7
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addx4 a7, a3, a7
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/* Retrieve previous owner (a8). */
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rsr a0, excsave1 # exc_table
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addx4 a0, a3, a0 # entry for CP
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l32i a8, a0, EXC_TABLE_COPROCESSOR_OWNER
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/* Set new owner (a9). */
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GET_THREAD_INFO (a9, a1)
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l32i a4, a9, THREAD_CPU
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s32i a9, a0, EXC_TABLE_COPROCESSOR_OWNER
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s32i a4, a9, THREAD_CP_OWNER_CPU
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/*
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* Enable coprocessor for the new owner. (a2 = 1 << CP number)
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* This can be done before loading context into the coprocessor.
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*/
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l32i a4, a9, THREAD_CPENABLE
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or a4, a4, a2
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/*
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* Make sure THREAD_CP_OWNER_CPU is in memory before updating
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* THREAD_CPENABLE
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*/
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memw # (2)
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s32i a4, a9, THREAD_CPENABLE
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beqz a8, 1f # skip 'save' if no previous owner
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/* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
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l32i a10, a8, THREAD_CPENABLE
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xor a10, a10, a2
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/* Get context save area and call save routine. */
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l32i a2, a7, CP_REGS_TAB_OFFSET
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l32i a3, a7, CP_REGS_TAB_SAVE
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add a2, a2, a8
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callx0 a3
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/*
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* Make sure coprocessor context and THREAD_CP_OWNER_CPU are in memory
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* before updating THREAD_CPENABLE
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*/
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memw # (3)
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s32i a10, a8, THREAD_CPENABLE
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1:
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/* Get context save area and call load routine. */
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l32i a2, a7, CP_REGS_TAB_OFFSET
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l32i a3, a7, CP_REGS_TAB_LOAD
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add a2, a2, a9
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callx0 a3
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/* Restore all registers and return from exception handler. */
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l32i a10, a1, PT_AREG10
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l32i a9, a1, PT_AREG9
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l32i a8, a1, PT_AREG8
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l32i a7, a1, PT_AREG7
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l32i a6, a1, PT_AREG6
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l32i a5, a1, PT_AREG5
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l32i a4, a1, PT_AREG4
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l32i a0, a1, PT_SAR
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l32i a3, a1, PT_AREG3
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l32i a2, a1, PT_AREG2
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wsr a0, sar
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l32i a0, a1, PT_AREG0
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l32i a1, a1, PT_AREG1
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rfe
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ENDPROC(fast_coprocessor)
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.text
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/*
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* coprocessor_flush(struct thread_info*, index)
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* a2 a3
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*
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* Save coprocessor registers for coprocessor 'index'.
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* The register values are saved to or loaded from the coprocessor area
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* inside the task_info structure.
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*
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* Note that this function doesn't update the coprocessor_owner information!
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*
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*/
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ENTRY(coprocessor_flush)
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abi_entry_default
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movi a4, .Lcp_regs_jump_table
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addx8 a4, a3, a4
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addx4 a3, a3, a4
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l32i a4, a3, CP_REGS_TAB_SAVE
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beqz a4, 1f
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l32i a3, a3, CP_REGS_TAB_OFFSET
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add a2, a2, a3
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mov a7, a0
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callx0 a4
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mov a0, a7
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1:
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abi_ret_default
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ENDPROC(coprocessor_flush)
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#endif /* XTENSA_HAVE_COPROCESSORS */
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