192 lines
5.4 KiB
C
192 lines
5.4 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2014-2018 Intel Corporation
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*/
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#include "intel_huc_fw.h"
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#include "i915_drv.h"
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/**
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* DOC: HuC Firmware
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*
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* Motivation:
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* GEN9 introduces a new dedicated firmware for usage in media HEVC (High
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* Efficiency Video Coding) operations. Userspace can use the firmware
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* capabilities by adding HuC specific commands to batch buffers.
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*
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* Implementation:
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* The same firmware loader is used as the GuC. However, the actual
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* loading to HW is deferred until GEM initialization is done.
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*
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* Note that HuC firmware loading must be done before GuC loading.
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*/
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#define BXT_HUC_FW_MAJOR 01
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#define BXT_HUC_FW_MINOR 8
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#define BXT_BLD_NUM 2893
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#define SKL_HUC_FW_MAJOR 01
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#define SKL_HUC_FW_MINOR 07
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#define SKL_BLD_NUM 1398
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#define KBL_HUC_FW_MAJOR 02
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#define KBL_HUC_FW_MINOR 00
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#define KBL_BLD_NUM 1810
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#define HUC_FW_PATH(platform, major, minor, bld_num) \
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"i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
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__stringify(minor) "_" __stringify(bld_num) ".bin"
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#define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
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SKL_HUC_FW_MINOR, SKL_BLD_NUM)
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MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
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#define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
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BXT_HUC_FW_MINOR, BXT_BLD_NUM)
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MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
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#define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
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KBL_HUC_FW_MINOR, KBL_BLD_NUM)
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MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
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static void huc_fw_select(struct intel_uc_fw *huc_fw)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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if (!HAS_HUC(dev_priv))
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return;
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if (i915_modparams.huc_firmware_path) {
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huc_fw->path = i915_modparams.huc_firmware_path;
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huc_fw->major_ver_wanted = 0;
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huc_fw->minor_ver_wanted = 0;
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} else if (IS_SKYLAKE(dev_priv)) {
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huc_fw->path = I915_SKL_HUC_UCODE;
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huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
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} else if (IS_BROXTON(dev_priv)) {
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huc_fw->path = I915_BXT_HUC_UCODE;
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huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
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} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
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huc_fw->path = I915_KBL_HUC_UCODE;
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huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
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huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
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}
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}
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/**
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* intel_huc_fw_init_early() - initializes HuC firmware struct
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* @huc: intel_huc struct
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*
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* On platforms with HuC selects firmware for uploading
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*/
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void intel_huc_fw_init_early(struct intel_huc *huc)
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{
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struct intel_uc_fw *huc_fw = &huc->fw;
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intel_uc_fw_init_early(huc_fw, INTEL_UC_FW_TYPE_HUC);
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huc_fw_select(huc_fw);
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}
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static void huc_xfer_rsa(struct intel_huc *huc)
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{
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struct intel_uc_fw *fw = &huc->fw;
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struct sg_table *pages = fw->obj->mm.pages;
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/*
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* HuC firmware image is outside GuC accessible range.
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* Copy the RSA signature out of the image into
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* the perma-pinned region set aside for it
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*/
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sg_pcopy_to_buffer(pages->sgl, pages->nents,
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huc->rsa_data_vaddr, fw->rsa_size,
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fw->rsa_offset);
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}
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static int huc_xfer_ucode(struct intel_huc *huc)
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{
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struct intel_uc_fw *huc_fw = &huc->fw;
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struct drm_i915_private *dev_priv = huc_to_i915(huc);
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struct intel_uncore *uncore = &dev_priv->uncore;
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unsigned long offset = 0;
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u32 size;
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int ret;
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GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
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intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
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/* Set the source address for the uCode */
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offset = intel_uc_fw_ggtt_offset(huc_fw) +
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huc_fw->header_offset;
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intel_uncore_write(uncore, DMA_ADDR_0_LOW,
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lower_32_bits(offset));
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intel_uncore_write(uncore, DMA_ADDR_0_HIGH,
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upper_32_bits(offset) & 0xFFFF);
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/*
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* Hardware doesn't look at destination address for HuC. Set it to 0,
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* but still program the correct address space.
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*/
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intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0);
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intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
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size = huc_fw->header_size + huc_fw->ucode_size;
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intel_uncore_write(uncore, DMA_COPY_SIZE, size);
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/* Start the DMA */
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intel_uncore_write(uncore, DMA_CTRL,
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_MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
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/* Wait for DMA to finish */
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ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
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DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
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/* Disable the bits once DMA is over */
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intel_uncore_write(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
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intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
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return ret;
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}
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/**
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* huc_fw_xfer() - DMA's the firmware
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* @huc_fw: the firmware descriptor
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*
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* Transfer the firmware image to RAM for execution by the microcontroller.
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*
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* Return: 0 on success, non-zero on failure
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*/
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static int huc_fw_xfer(struct intel_uc_fw *huc_fw)
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{
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struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
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huc_xfer_rsa(huc);
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return huc_xfer_ucode(huc);
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}
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/**
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* intel_huc_fw_upload() - load HuC uCode to device
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* @huc: intel_huc structure
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*
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* Called from intel_uc_init_hw() during driver load, resume from sleep and
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* after a GPU reset. Note that HuC must be loaded before GuC.
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*
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* The firmware image should have already been fetched into memory, so only
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* check that fetch succeeded, and then transfer the image to the h/w.
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*
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* Return: non-zero code on error
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*/
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int intel_huc_fw_upload(struct intel_huc *huc)
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{
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return intel_uc_fw_upload(&huc->fw, huc_fw_xfer);
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}
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