210 lines
5.1 KiB
C
210 lines
5.1 KiB
C
/*
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* This file contains common code that is intended to be used across
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* boards so that it's not replicated.
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/cpumask.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/zynq.h>
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#include <linux/clocksource.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of.h>
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#include <linux/memblock.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach-types.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/smp_scu.h>
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#include <asm/system_info.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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#define ZYNQ_DEVCFG_MCTRL 0x80
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#define ZYNQ_DEVCFG_PS_VERSION_SHIFT 28
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#define ZYNQ_DEVCFG_PS_VERSION_MASK 0xF
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void __iomem *zynq_scu_base;
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/**
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* zynq_memory_init - Initialize special memory
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*
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* We need to stop things allocating the low memory as DMA can't work in
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* the 1st 512K of memory.
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*/
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static void __init zynq_memory_init(void)
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{
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if (!__pa(PAGE_OFFSET))
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memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir));
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}
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static struct platform_device zynq_cpuidle_device = {
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.name = "cpuidle-zynq",
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};
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/**
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* zynq_get_revision - Get Zynq silicon revision
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*
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* Return: Silicon version or -1 otherwise
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*/
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static int __init zynq_get_revision(void)
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{
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struct device_node *np;
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void __iomem *zynq_devcfg_base;
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u32 revision;
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np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
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if (!np) {
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pr_err("%s: no devcfg node found\n", __func__);
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return -1;
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}
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zynq_devcfg_base = of_iomap(np, 0);
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if (!zynq_devcfg_base) {
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pr_err("%s: Unable to map I/O memory\n", __func__);
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return -1;
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}
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revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
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revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
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revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
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iounmap(zynq_devcfg_base);
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return revision;
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}
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static void __init zynq_init_late(void)
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{
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zynq_core_pm_init();
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zynq_pm_late_init();
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}
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/**
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* zynq_init_machine - System specific initialization, intended to be
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* called from board specific initialization.
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*/
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static void __init zynq_init_machine(void)
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{
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struct platform_device_info devinfo = { .name = "cpufreq-dt", };
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struct soc_device_attribute *soc_dev_attr;
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struct soc_device *soc_dev;
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struct device *parent = NULL;
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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goto out;
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system_rev = zynq_get_revision();
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soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
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soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
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zynq_slcr_get_device_id());
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->family);
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr->soc_id);
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kfree(soc_dev_attr);
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goto out;
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}
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parent = soc_device_to_device(soc_dev);
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out:
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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platform_device_register(&zynq_cpuidle_device);
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platform_device_register_full(&devinfo);
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}
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static void __init zynq_timer_init(void)
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{
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zynq_early_slcr_init();
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zynq_clock_init();
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of_clk_init(NULL);
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clocksource_probe();
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}
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static struct map_desc zynq_cortex_a9_scu_map __initdata = {
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.length = SZ_256,
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.type = MT_DEVICE,
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};
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static void __init zynq_scu_map_io(void)
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{
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unsigned long base;
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base = scu_a9_get_base();
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zynq_cortex_a9_scu_map.pfn = __phys_to_pfn(base);
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/* Expected address is in vmalloc area that's why simple assign here */
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zynq_cortex_a9_scu_map.virtual = base;
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iotable_init(&zynq_cortex_a9_scu_map, 1);
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zynq_scu_base = (void __iomem *)base;
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BUG_ON(!zynq_scu_base);
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}
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/**
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* zynq_map_io - Create memory mappings needed for early I/O.
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*/
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static void __init zynq_map_io(void)
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{
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debug_ll_io_init();
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zynq_scu_map_io();
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}
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static void __init zynq_irq_init(void)
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{
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irqchip_init();
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}
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static const char * const zynq_dt_match[] = {
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"xlnx,zynq-7000",
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NULL
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};
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DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
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/* 64KB way size, 8-way associativity, parity disabled */
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.l2c_aux_val = 0x00400000,
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.l2c_aux_mask = 0xffbfffff,
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.smp = smp_ops(zynq_smp_ops),
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.map_io = zynq_map_io,
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.init_irq = zynq_irq_init,
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.init_machine = zynq_init_machine,
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.init_late = zynq_init_late,
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.init_time = zynq_timer_init,
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.dt_compat = zynq_dt_match,
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.reserve = zynq_memory_init,
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MACHINE_END
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