881 lines
29 KiB
C
881 lines
29 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_audio.h"
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#include "atom.h"
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#include "rs690d.h"
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int rs690_mc_wait_for_idle(struct radeon_device *rdev)
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{
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unsigned i;
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uint32_t tmp;
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
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if (G_000090_MC_SYSTEM_IDLE(tmp))
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return 0;
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udelay(1);
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}
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return -1;
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}
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static void rs690_gpu_init(struct radeon_device *rdev)
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{
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/* FIXME: is this correct ? */
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r420_pipes_init(rdev);
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if (rs690_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "Failed to wait MC idle while "
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"programming pipes. Bad things might happen.\n");
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}
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}
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union igp_info {
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struct _ATOM_INTEGRATED_SYSTEM_INFO info;
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struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
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};
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void rs690_pm_info(struct radeon_device *rdev)
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{
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int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
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union igp_info *info;
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uint16_t data_offset;
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uint8_t frev, crev;
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fixed20_12 tmp;
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if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
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&frev, &crev, &data_offset)) {
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info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
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/* Get various system informations from bios */
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switch (crev) {
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case 1:
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tmp.full = dfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock));
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rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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if (le16_to_cpu(info->info.usK8MemoryClock))
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rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
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else if (rdev->clock.default_mclk) {
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rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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} else
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rdev->pm.igp_system_mclk.full = dfixed_const(400);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
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rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
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break;
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case 2:
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tmp.full = dfixed_const(100);
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rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock));
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rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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if (le32_to_cpu(info->info_v2.ulBootUpUMAClock))
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rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock));
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else if (rdev->clock.default_mclk)
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rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
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else
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rdev->pm.igp_system_mclk.full = dfixed_const(66700);
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rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq));
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rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
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rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
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break;
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default:
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/* We assume the slower possible clock ie worst case */
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rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
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rdev->pm.igp_system_mclk.full = dfixed_const(200);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
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rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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break;
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}
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} else {
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/* We assume the slower possible clock ie worst case */
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rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
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rdev->pm.igp_system_mclk.full = dfixed_const(200);
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rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
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rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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}
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/* Compute various bandwidth */
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/* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
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tmp.full = dfixed_const(4);
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rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
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/* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
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* = ht_clk * ht_width / 5
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*/
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tmp.full = dfixed_const(5);
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rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
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rdev->pm.igp_ht_link_width);
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rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
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if (tmp.full < rdev->pm.max_bandwidth.full) {
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/* HT link is a limiting factor */
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rdev->pm.max_bandwidth.full = tmp.full;
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}
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/* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
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* = (sideport_clk * 14) / 10
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*/
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tmp.full = dfixed_const(14);
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rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
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tmp.full = dfixed_const(10);
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rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
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}
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static void rs690_mc_init(struct radeon_device *rdev)
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{
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u64 base;
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uint32_t h_addr, l_addr;
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unsigned long long k8_addr;
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rs400_gart_adjust_size(rdev);
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
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rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
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base = G_000100_MC_FB_START(base) << 16;
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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/* Some boards seem to be configured for 128MB of sideport memory,
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* but really only have 64MB. Just skip the sideport and use
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* UMA memory.
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*/
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if (rdev->mc.igp_sideport_enabled &&
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(rdev->mc.real_vram_size == (384 * 1024 * 1024))) {
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base += 128 * 1024 * 1024;
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rdev->mc.real_vram_size -= 128 * 1024 * 1024;
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rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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}
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/* Use K8 direct mapping for fast fb access. */
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rdev->fastfb_working = false;
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h_addr = G_00005F_K8_ADDR_EXT(RREG32_MC(R_00005F_MC_MISC_UMA_CNTL));
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l_addr = RREG32_MC(R_00001E_K8_FB_LOCATION);
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k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
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#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
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if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
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#endif
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{
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/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
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* memory is present.
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*/
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if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
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DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
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(unsigned long long)rdev->mc.aper_base, k8_addr);
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rdev->mc.aper_base = (resource_size_t)k8_addr;
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rdev->fastfb_working = true;
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}
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}
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rs690_pm_info(rdev);
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radeon_vram_location(rdev, &rdev->mc, base);
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rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
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radeon_gtt_location(rdev, &rdev->mc);
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radeon_update_bandwidth_info(rdev);
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}
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void rs690_line_buffer_adjust(struct radeon_device *rdev,
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struct drm_display_mode *mode1,
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struct drm_display_mode *mode2)
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{
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u32 tmp;
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/* Guess line buffer size to be 8192 pixels */
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u32 lb_size = 8192;
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/*
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* Line Buffer Setup
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* There is a single line buffer shared by both display controllers.
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* R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
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* the display controllers. The paritioning can either be done
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* manually or via one of four preset allocations specified in bits 1:0:
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* 0 - line buffer is divided in half and shared between crtc
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* 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
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* 2 - D1 gets the whole buffer
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* 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
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* Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
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* allocation mode. In manual allocation mode, D1 always starts at 0,
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* D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
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*/
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tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
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tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
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/* auto */
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if (mode1 && mode2) {
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if (mode1->hdisplay > mode2->hdisplay) {
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if (mode1->hdisplay > 2560)
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
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else
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else if (mode2->hdisplay > mode1->hdisplay) {
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if (mode2->hdisplay > 2560)
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
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else
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
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} else if (mode1) {
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
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} else if (mode2) {
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tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
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}
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WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
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/* Save number of lines the linebuffer leads before the scanout */
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if (mode1)
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rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
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if (mode2)
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rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
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}
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struct rs690_watermark {
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u32 lb_request_fifo_depth;
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fixed20_12 num_line_pair;
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fixed20_12 estimated_width;
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fixed20_12 worst_case_latency;
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fixed20_12 consumption_rate;
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fixed20_12 active_time;
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fixed20_12 dbpp;
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fixed20_12 priority_mark_max;
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fixed20_12 priority_mark;
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fixed20_12 sclk;
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};
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static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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struct radeon_crtc *crtc,
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struct rs690_watermark *wm,
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bool low)
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{
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struct drm_display_mode *mode = &crtc->base.mode;
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fixed20_12 a, b, c;
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fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
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fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
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fixed20_12 sclk, core_bandwidth, max_bandwidth;
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u32 selected_sclk;
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if (!crtc->base.enabled) {
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/* FIXME: wouldn't it better to set priority mark to maximum */
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wm->lb_request_fifo_depth = 4;
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return;
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}
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if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
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(rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
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selected_sclk = radeon_dpm_get_sclk(rdev, low);
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else
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selected_sclk = rdev->pm.current_sclk;
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/* sclk in Mhz */
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a.full = dfixed_const(100);
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sclk.full = dfixed_const(selected_sclk);
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sclk.full = dfixed_div(sclk, a);
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/* core_bandwidth = sclk(Mhz) * 16 */
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a.full = dfixed_const(16);
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core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
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if (crtc->vsc.full > dfixed_const(2))
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wm->num_line_pair.full = dfixed_const(2);
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else
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wm->num_line_pair.full = dfixed_const(1);
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b.full = dfixed_const(mode->crtc_hdisplay);
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c.full = dfixed_const(256);
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a.full = dfixed_div(b, c);
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request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
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request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
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if (a.full < dfixed_const(4)) {
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wm->lb_request_fifo_depth = 4;
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} else {
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wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
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}
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/* Determine consumption rate
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* pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
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* vtaps = number of vertical taps,
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* vsc = vertical scaling ratio, defined as source/destination
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* hsc = horizontal scaling ration, defined as source/destination
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*/
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a.full = dfixed_const(mode->clock);
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b.full = dfixed_const(1000);
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a.full = dfixed_div(a, b);
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pclk.full = dfixed_div(b, a);
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if (crtc->rmx_type != RMX_OFF) {
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b.full = dfixed_const(2);
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if (crtc->vsc.full > b.full)
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b.full = crtc->vsc.full;
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b.full = dfixed_mul(b, crtc->hsc);
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c.full = dfixed_const(2);
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b.full = dfixed_div(b, c);
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consumption_time.full = dfixed_div(pclk, b);
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} else {
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consumption_time.full = pclk.full;
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}
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a.full = dfixed_const(1);
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wm->consumption_rate.full = dfixed_div(a, consumption_time);
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/* Determine line time
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* LineTime = total time for one line of displayhtotal
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* LineTime = total number of horizontal pixels
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* pclk = pixel clock period(ns)
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*/
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a.full = dfixed_const(crtc->base.mode.crtc_htotal);
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line_time.full = dfixed_mul(a, pclk);
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/* Determine active time
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* ActiveTime = time of active region of display within one line,
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* hactive = total number of horizontal active pixels
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* htotal = total number of horizontal pixels
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*/
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a.full = dfixed_const(crtc->base.mode.crtc_htotal);
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b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
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wm->active_time.full = dfixed_mul(line_time, b);
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wm->active_time.full = dfixed_div(wm->active_time, a);
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/* Maximun bandwidth is the minimun bandwidth of all component */
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max_bandwidth = core_bandwidth;
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if (rdev->mc.igp_sideport_enabled) {
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if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
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rdev->pm.sideport_bandwidth.full)
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max_bandwidth = rdev->pm.sideport_bandwidth;
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read_delay_latency.full = dfixed_const(370 * 800);
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a.full = dfixed_const(1000);
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b.full = dfixed_div(rdev->pm.igp_sideport_mclk, a);
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read_delay_latency.full = dfixed_div(read_delay_latency, b);
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read_delay_latency.full = dfixed_mul(read_delay_latency, a);
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} else {
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if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
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rdev->pm.k8_bandwidth.full)
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max_bandwidth = rdev->pm.k8_bandwidth;
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if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
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rdev->pm.ht_bandwidth.full)
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max_bandwidth = rdev->pm.ht_bandwidth;
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read_delay_latency.full = dfixed_const(5000);
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}
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/* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
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a.full = dfixed_const(16);
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sclk.full = dfixed_mul(max_bandwidth, a);
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a.full = dfixed_const(1000);
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sclk.full = dfixed_div(a, sclk);
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/* Determine chunk time
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* ChunkTime = the time it takes the DCP to send one chunk of data
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* to the LB which consists of pipeline delay and inter chunk gap
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* sclk = system clock(ns)
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*/
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a.full = dfixed_const(256 * 13);
|
|
chunk_time.full = dfixed_mul(sclk, a);
|
|
a.full = dfixed_const(10);
|
|
chunk_time.full = dfixed_div(chunk_time, a);
|
|
|
|
/* Determine the worst case latency
|
|
* NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
|
|
* WorstCaseLatency = worst case time from urgent to when the MC starts
|
|
* to return data
|
|
* READ_DELAY_IDLE_MAX = constant of 1us
|
|
* ChunkTime = time it takes the DCP to send one chunk of data to the LB
|
|
* which consists of pipeline delay and inter chunk gap
|
|
*/
|
|
if (dfixed_trunc(wm->num_line_pair) > 1) {
|
|
a.full = dfixed_const(3);
|
|
wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
|
|
wm->worst_case_latency.full += read_delay_latency.full;
|
|
} else {
|
|
a.full = dfixed_const(2);
|
|
wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
|
|
wm->worst_case_latency.full += read_delay_latency.full;
|
|
}
|
|
|
|
/* Determine the tolerable latency
|
|
* TolerableLatency = Any given request has only 1 line time
|
|
* for the data to be returned
|
|
* LBRequestFifoDepth = Number of chunk requests the LB can
|
|
* put into the request FIFO for a display
|
|
* LineTime = total time for one line of display
|
|
* ChunkTime = the time it takes the DCP to send one chunk
|
|
* of data to the LB which consists of
|
|
* pipeline delay and inter chunk gap
|
|
*/
|
|
if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
|
|
tolerable_latency.full = line_time.full;
|
|
} else {
|
|
tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
|
|
tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
|
|
tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
|
|
tolerable_latency.full = line_time.full - tolerable_latency.full;
|
|
}
|
|
/* We assume worst case 32bits (4 bytes) */
|
|
wm->dbpp.full = dfixed_const(4 * 8);
|
|
|
|
/* Determine the maximum priority mark
|
|
* width = viewport width in pixels
|
|
*/
|
|
a.full = dfixed_const(16);
|
|
wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
|
|
wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
|
|
wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
|
|
|
|
/* Determine estimated width */
|
|
estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
|
|
estimated_width.full = dfixed_div(estimated_width, consumption_time);
|
|
if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
|
|
wm->priority_mark.full = dfixed_const(10);
|
|
} else {
|
|
a.full = dfixed_const(16);
|
|
wm->priority_mark.full = dfixed_div(estimated_width, a);
|
|
wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
|
|
wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
|
|
}
|
|
}
|
|
|
|
static void rs690_compute_mode_priority(struct radeon_device *rdev,
|
|
struct rs690_watermark *wm0,
|
|
struct rs690_watermark *wm1,
|
|
struct drm_display_mode *mode0,
|
|
struct drm_display_mode *mode1,
|
|
u32 *d1mode_priority_a_cnt,
|
|
u32 *d2mode_priority_a_cnt)
|
|
{
|
|
fixed20_12 priority_mark02, priority_mark12, fill_rate;
|
|
fixed20_12 a, b;
|
|
|
|
*d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
|
|
*d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
|
|
|
|
if (mode0 && mode1) {
|
|
if (dfixed_trunc(wm0->dbpp) > 64)
|
|
a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
|
|
else
|
|
a.full = wm0->num_line_pair.full;
|
|
if (dfixed_trunc(wm1->dbpp) > 64)
|
|
b.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
|
|
else
|
|
b.full = wm1->num_line_pair.full;
|
|
a.full += b.full;
|
|
fill_rate.full = dfixed_div(wm0->sclk, a);
|
|
if (wm0->consumption_rate.full > fill_rate.full) {
|
|
b.full = wm0->consumption_rate.full - fill_rate.full;
|
|
b.full = dfixed_mul(b, wm0->active_time);
|
|
a.full = dfixed_mul(wm0->worst_case_latency,
|
|
wm0->consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark02.full = dfixed_div(a, b);
|
|
} else {
|
|
a.full = dfixed_mul(wm0->worst_case_latency,
|
|
wm0->consumption_rate);
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark02.full = dfixed_div(a, b);
|
|
}
|
|
if (wm1->consumption_rate.full > fill_rate.full) {
|
|
b.full = wm1->consumption_rate.full - fill_rate.full;
|
|
b.full = dfixed_mul(b, wm1->active_time);
|
|
a.full = dfixed_mul(wm1->worst_case_latency,
|
|
wm1->consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark12.full = dfixed_div(a, b);
|
|
} else {
|
|
a.full = dfixed_mul(wm1->worst_case_latency,
|
|
wm1->consumption_rate);
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark12.full = dfixed_div(a, b);
|
|
}
|
|
if (wm0->priority_mark.full > priority_mark02.full)
|
|
priority_mark02.full = wm0->priority_mark.full;
|
|
if (wm0->priority_mark_max.full > priority_mark02.full)
|
|
priority_mark02.full = wm0->priority_mark_max.full;
|
|
if (wm1->priority_mark.full > priority_mark12.full)
|
|
priority_mark12.full = wm1->priority_mark.full;
|
|
if (wm1->priority_mark_max.full > priority_mark12.full)
|
|
priority_mark12.full = wm1->priority_mark_max.full;
|
|
*d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
|
|
*d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
|
|
if (rdev->disp_priority == 2) {
|
|
*d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
*d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
}
|
|
} else if (mode0) {
|
|
if (dfixed_trunc(wm0->dbpp) > 64)
|
|
a.full = dfixed_mul(wm0->dbpp, wm0->num_line_pair);
|
|
else
|
|
a.full = wm0->num_line_pair.full;
|
|
fill_rate.full = dfixed_div(wm0->sclk, a);
|
|
if (wm0->consumption_rate.full > fill_rate.full) {
|
|
b.full = wm0->consumption_rate.full - fill_rate.full;
|
|
b.full = dfixed_mul(b, wm0->active_time);
|
|
a.full = dfixed_mul(wm0->worst_case_latency,
|
|
wm0->consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark02.full = dfixed_div(a, b);
|
|
} else {
|
|
a.full = dfixed_mul(wm0->worst_case_latency,
|
|
wm0->consumption_rate);
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark02.full = dfixed_div(a, b);
|
|
}
|
|
if (wm0->priority_mark.full > priority_mark02.full)
|
|
priority_mark02.full = wm0->priority_mark.full;
|
|
if (wm0->priority_mark_max.full > priority_mark02.full)
|
|
priority_mark02.full = wm0->priority_mark_max.full;
|
|
*d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
|
|
if (rdev->disp_priority == 2)
|
|
*d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
} else if (mode1) {
|
|
if (dfixed_trunc(wm1->dbpp) > 64)
|
|
a.full = dfixed_mul(wm1->dbpp, wm1->num_line_pair);
|
|
else
|
|
a.full = wm1->num_line_pair.full;
|
|
fill_rate.full = dfixed_div(wm1->sclk, a);
|
|
if (wm1->consumption_rate.full > fill_rate.full) {
|
|
b.full = wm1->consumption_rate.full - fill_rate.full;
|
|
b.full = dfixed_mul(b, wm1->active_time);
|
|
a.full = dfixed_mul(wm1->worst_case_latency,
|
|
wm1->consumption_rate);
|
|
a.full = a.full + b.full;
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark12.full = dfixed_div(a, b);
|
|
} else {
|
|
a.full = dfixed_mul(wm1->worst_case_latency,
|
|
wm1->consumption_rate);
|
|
b.full = dfixed_const(16 * 1000);
|
|
priority_mark12.full = dfixed_div(a, b);
|
|
}
|
|
if (wm1->priority_mark.full > priority_mark12.full)
|
|
priority_mark12.full = wm1->priority_mark.full;
|
|
if (wm1->priority_mark_max.full > priority_mark12.full)
|
|
priority_mark12.full = wm1->priority_mark_max.full;
|
|
*d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
|
|
if (rdev->disp_priority == 2)
|
|
*d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
}
|
|
}
|
|
|
|
void rs690_bandwidth_update(struct radeon_device *rdev)
|
|
{
|
|
struct drm_display_mode *mode0 = NULL;
|
|
struct drm_display_mode *mode1 = NULL;
|
|
struct rs690_watermark wm0_high, wm0_low;
|
|
struct rs690_watermark wm1_high, wm1_low;
|
|
u32 tmp;
|
|
u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
|
|
u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
|
|
|
|
if (!rdev->mode_info.mode_config_initialized)
|
|
return;
|
|
|
|
radeon_update_display_priority(rdev);
|
|
|
|
if (rdev->mode_info.crtcs[0]->base.enabled)
|
|
mode0 = &rdev->mode_info.crtcs[0]->base.mode;
|
|
if (rdev->mode_info.crtcs[1]->base.enabled)
|
|
mode1 = &rdev->mode_info.crtcs[1]->base.mode;
|
|
/*
|
|
* Set display0/1 priority up in the memory controller for
|
|
* modes if the user specifies HIGH for displaypriority
|
|
* option.
|
|
*/
|
|
if ((rdev->disp_priority == 2) &&
|
|
((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
|
|
tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
|
|
tmp &= C_000104_MC_DISP0R_INIT_LAT;
|
|
tmp &= C_000104_MC_DISP1R_INIT_LAT;
|
|
if (mode0)
|
|
tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
|
|
if (mode1)
|
|
tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
|
|
WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
|
|
}
|
|
rs690_line_buffer_adjust(rdev, mode0, mode1);
|
|
|
|
if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
|
|
WREG32(R_006C9C_DCP_CONTROL, 0);
|
|
if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
|
|
WREG32(R_006C9C_DCP_CONTROL, 2);
|
|
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
|
|
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true);
|
|
rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true);
|
|
|
|
tmp = (wm0_high.lb_request_fifo_depth - 1);
|
|
tmp |= (wm1_high.lb_request_fifo_depth - 1) << 16;
|
|
WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
|
|
|
|
rs690_compute_mode_priority(rdev,
|
|
&wm0_high, &wm1_high,
|
|
mode0, mode1,
|
|
&d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
|
|
rs690_compute_mode_priority(rdev,
|
|
&wm0_low, &wm1_low,
|
|
mode0, mode1,
|
|
&d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
|
|
|
|
WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
|
|
WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
|
|
WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
|
|
WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
|
|
}
|
|
|
|
uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
unsigned long flags;
|
|
uint32_t r;
|
|
|
|
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
|
|
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
|
|
r = RREG32(R_00007C_MC_DATA);
|
|
WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
|
|
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
|
|
return r;
|
|
}
|
|
|
|
void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&rdev->mc_idx_lock, flags);
|
|
WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
|
|
S_000078_MC_IND_WR_EN(1));
|
|
WREG32(R_00007C_MC_DATA, v);
|
|
WREG32(R_000078_MC_INDEX, 0x7F);
|
|
spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
|
|
}
|
|
|
|
static void rs690_mc_program(struct radeon_device *rdev)
|
|
{
|
|
struct rv515_mc_save save;
|
|
|
|
/* Stops all mc clients */
|
|
rv515_mc_stop(rdev, &save);
|
|
|
|
/* Wait for mc idle */
|
|
if (rs690_mc_wait_for_idle(rdev))
|
|
dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
|
|
/* Program MC, should be a 32bits limited address space */
|
|
WREG32_MC(R_000100_MCCFG_FB_LOCATION,
|
|
S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
|
|
S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
|
|
WREG32(R_000134_HDP_FB_LOCATION,
|
|
S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
|
|
|
|
rv515_mc_resume(rdev, &save);
|
|
}
|
|
|
|
static int rs690_startup(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
rs690_mc_program(rdev);
|
|
/* Resume clock */
|
|
rv515_clock_startup(rdev);
|
|
/* Initialize GPU configuration (# pipes, ...) */
|
|
rs690_gpu_init(rdev);
|
|
/* Initialize GART (initialize after TTM so we can allocate
|
|
* memory through TTM but finalize after TTM) */
|
|
r = rs400_gart_enable(rdev);
|
|
if (r)
|
|
return r;
|
|
|
|
/* allocate wb buffer */
|
|
r = radeon_wb_init(rdev);
|
|
if (r)
|
|
return r;
|
|
|
|
r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
|
if (r) {
|
|
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
/* Enable IRQ */
|
|
if (!rdev->irq.installed) {
|
|
r = radeon_irq_kms_init(rdev);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
rs600_irq_set(rdev);
|
|
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
|
|
/* 1M ring buffer */
|
|
r = r100_cp_init(rdev, 1024 * 1024);
|
|
if (r) {
|
|
dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
r = radeon_ib_pool_init(rdev);
|
|
if (r) {
|
|
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
|
|
return r;
|
|
}
|
|
|
|
r = radeon_audio_init(rdev);
|
|
if (r) {
|
|
dev_err(rdev->dev, "failed initializing audio\n");
|
|
return r;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int rs690_resume(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
/* Make sur GART are not working */
|
|
rs400_gart_disable(rdev);
|
|
/* Resume clock before doing reset */
|
|
rv515_clock_startup(rdev);
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_asic_reset(rdev)) {
|
|
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
RREG32(R_0007C0_CP_STAT));
|
|
}
|
|
/* post */
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
/* Resume clock after posting */
|
|
rv515_clock_startup(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
|
|
rdev->accel_working = true;
|
|
r = rs690_startup(rdev);
|
|
if (r) {
|
|
rdev->accel_working = false;
|
|
}
|
|
return r;
|
|
}
|
|
|
|
int rs690_suspend(struct radeon_device *rdev)
|
|
{
|
|
radeon_pm_suspend(rdev);
|
|
radeon_audio_fini(rdev);
|
|
r100_cp_disable(rdev);
|
|
radeon_wb_disable(rdev);
|
|
rs600_irq_disable(rdev);
|
|
rs400_gart_disable(rdev);
|
|
return 0;
|
|
}
|
|
|
|
void rs690_fini(struct radeon_device *rdev)
|
|
{
|
|
radeon_pm_fini(rdev);
|
|
radeon_audio_fini(rdev);
|
|
r100_cp_fini(rdev);
|
|
radeon_wb_fini(rdev);
|
|
radeon_ib_pool_fini(rdev);
|
|
radeon_gem_fini(rdev);
|
|
rs400_gart_fini(rdev);
|
|
radeon_irq_kms_fini(rdev);
|
|
radeon_fence_driver_fini(rdev);
|
|
radeon_bo_fini(rdev);
|
|
radeon_atombios_fini(rdev);
|
|
kfree(rdev->bios);
|
|
rdev->bios = NULL;
|
|
}
|
|
|
|
int rs690_init(struct radeon_device *rdev)
|
|
{
|
|
int r;
|
|
|
|
/* Disable VGA */
|
|
rv515_vga_render_disable(rdev);
|
|
/* Initialize scratch registers */
|
|
radeon_scratch_init(rdev);
|
|
/* Initialize surface registers */
|
|
radeon_surface_init(rdev);
|
|
/* restore some register to sane defaults */
|
|
r100_restore_sanity(rdev);
|
|
/* TODO: disable VGA need to use VGA request */
|
|
/* BIOS*/
|
|
if (!radeon_get_bios(rdev)) {
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
return -EINVAL;
|
|
}
|
|
if (rdev->is_atom_bios) {
|
|
r = radeon_atombios_init(rdev);
|
|
if (r)
|
|
return r;
|
|
} else {
|
|
dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
|
|
return -EINVAL;
|
|
}
|
|
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
|
|
if (radeon_asic_reset(rdev)) {
|
|
dev_warn(rdev->dev,
|
|
"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
|
|
RREG32(R_000E40_RBBM_STATUS),
|
|
RREG32(R_0007C0_CP_STAT));
|
|
}
|
|
/* check if cards are posted or not */
|
|
if (radeon_boot_test_post_card(rdev) == false)
|
|
return -EINVAL;
|
|
|
|
/* Initialize clocks */
|
|
radeon_get_clock_info(rdev->ddev);
|
|
/* initialize memory controller */
|
|
rs690_mc_init(rdev);
|
|
rv515_debugfs(rdev);
|
|
/* Fence driver */
|
|
r = radeon_fence_driver_init(rdev);
|
|
if (r)
|
|
return r;
|
|
/* Memory manager */
|
|
r = radeon_bo_init(rdev);
|
|
if (r)
|
|
return r;
|
|
r = rs400_gart_init(rdev);
|
|
if (r)
|
|
return r;
|
|
rs600_set_safe_registers(rdev);
|
|
|
|
/* Initialize power management */
|
|
radeon_pm_init(rdev);
|
|
|
|
rdev->accel_working = true;
|
|
r = rs690_startup(rdev);
|
|
if (r) {
|
|
/* Somethings want wront with the accel init stop accel */
|
|
dev_err(rdev->dev, "Disabling GPU acceleration\n");
|
|
r100_cp_fini(rdev);
|
|
radeon_wb_fini(rdev);
|
|
radeon_ib_pool_fini(rdev);
|
|
rs400_gart_fini(rdev);
|
|
radeon_irq_kms_fini(rdev);
|
|
rdev->accel_working = false;
|
|
}
|
|
return 0;
|
|
}
|