285 lines
6.8 KiB
C
285 lines
6.8 KiB
C
/*
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* r8a7790 Common Clock Framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define CPG_DIV6_CKSTP BIT(8)
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#define CPG_DIV6_DIV(d) ((d) & 0x3f)
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#define CPG_DIV6_DIV_MASK 0x3f
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/**
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* struct div6_clock - CPG 6 bit divider clock
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* @hw: handle between common and hardware-specific interfaces
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* @reg: IO-remapped register
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* @div: divisor value (1-64)
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*/
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struct div6_clock {
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struct clk_hw hw;
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void __iomem *reg;
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unsigned int div;
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u32 src_shift;
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u32 src_width;
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u8 *parents;
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};
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#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
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static int cpg_div6_clock_enable(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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u32 val;
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val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
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| CPG_DIV6_DIV(clock->div - 1);
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clk_writel(val, clock->reg);
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return 0;
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}
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static void cpg_div6_clock_disable(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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u32 val;
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val = clk_readl(clock->reg);
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val |= CPG_DIV6_CKSTP;
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/*
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* DIV6 clocks require the divisor field to be non-zero when stopping
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* the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
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* re-enabled later if the divisor field is changed when stopping the
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* clock
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*/
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if (!(val & CPG_DIV6_DIV_MASK))
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val |= CPG_DIV6_DIV_MASK;
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clk_writel(val, clock->reg);
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}
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static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
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}
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static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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return parent_rate / div;
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}
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static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
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unsigned long parent_rate)
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{
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unsigned int div;
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if (!rate)
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rate = 1;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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return clamp_t(unsigned int, div, 1, 64);
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}
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static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
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return *parent_rate / div;
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}
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static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
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u32 val;
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clock->div = div;
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val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
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/* Only program the new divisor if the clock isn't stopped. */
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if (!(val & CPG_DIV6_CKSTP))
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clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
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return 0;
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}
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static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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unsigned int i;
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u8 hw_index;
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if (clock->src_width == 0)
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return 0;
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hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
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(BIT(clock->src_width) - 1);
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for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
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if (clock->parents[i] == hw_index)
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return i;
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}
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pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
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__func__, __clk_get_name(hw->clk), hw_index);
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return 0;
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}
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static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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u8 hw_index;
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u32 mask;
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if (index >= __clk_get_num_parents(hw->clk))
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return -EINVAL;
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mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
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hw_index = clock->parents[index];
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clk_writel((clk_readl(clock->reg) & mask) |
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(hw_index << clock->src_shift), clock->reg);
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return 0;
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}
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static const struct clk_ops cpg_div6_clock_ops = {
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.enable = cpg_div6_clock_enable,
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.disable = cpg_div6_clock_disable,
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.is_enabled = cpg_div6_clock_is_enabled,
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.get_parent = cpg_div6_clock_get_parent,
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.set_parent = cpg_div6_clock_set_parent,
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.recalc_rate = cpg_div6_clock_recalc_rate,
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.round_rate = cpg_div6_clock_round_rate,
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.set_rate = cpg_div6_clock_set_rate,
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};
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static void __init cpg_div6_clock_init(struct device_node *np)
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{
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unsigned int num_parents, valid_parents;
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const char **parent_names;
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struct clk_init_data init;
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struct div6_clock *clock;
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const char *name;
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struct clk *clk;
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unsigned int i;
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int ret;
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clock = kzalloc(sizeof(*clock), GFP_KERNEL);
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if (!clock)
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return;
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num_parents = of_clk_get_parent_count(np);
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if (num_parents < 1) {
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pr_err("%s: no parent found for %s DIV6 clock\n",
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__func__, np->name);
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return;
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}
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clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
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GFP_KERNEL);
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parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
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GFP_KERNEL);
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if (!parent_names)
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return;
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/* Remap the clock register and read the divisor. Disabling the
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* clock overwrites the divisor, so we need to cache its value for the
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* enable operation.
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*/
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clock->reg = of_iomap(np, 0);
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if (clock->reg == NULL) {
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pr_err("%s: failed to map %s DIV6 clock register\n",
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__func__, np->name);
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goto error;
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}
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clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
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/* Parse the DT properties. */
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ret = of_property_read_string(np, "clock-output-names", &name);
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if (ret < 0) {
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pr_err("%s: failed to get %s DIV6 clock output name\n",
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__func__, np->name);
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goto error;
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}
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for (i = 0, valid_parents = 0; i < num_parents; i++) {
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const char *name = of_clk_get_parent_name(np, i);
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if (name) {
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parent_names[valid_parents] = name;
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clock->parents[valid_parents] = i;
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valid_parents++;
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}
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}
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switch (num_parents) {
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case 1:
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/* fixed parent clock */
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clock->src_shift = clock->src_width = 0;
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break;
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case 4:
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/* clock with EXSRC bits 6-7 */
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clock->src_shift = 6;
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clock->src_width = 2;
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break;
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case 8:
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/* VCLK with EXSRC bits 12-14 */
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clock->src_shift = 12;
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clock->src_width = 3;
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break;
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default:
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pr_err("%s: invalid number of parents for DIV6 clock %s\n",
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__func__, np->name);
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goto error;
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}
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/* Register the clock. */
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init.name = name;
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init.ops = &cpg_div6_clock_ops;
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init.flags = CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = valid_parents;
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clock->hw.init = &init;
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clk = clk_register(NULL, &clock->hw);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
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__func__, np->name, PTR_ERR(clk));
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goto error;
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}
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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kfree(parent_names);
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return;
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error:
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if (clock->reg)
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iounmap(clock->reg);
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kfree(parent_names);
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kfree(clock);
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}
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CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);
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