317 lines
7.9 KiB
C
317 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021, ASPEED Technology Inc.
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// Authors: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com>
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#include <linux/firmware.h>
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#include <linux/delay.h>
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#include <drm/drm_print.h>
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#include "ast_drv.h"
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int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata)
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{
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struct ast_private *ast = to_ast_private(dev);
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u8 i = 0, j = 0;
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/*
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* CRD1[b5]: DP MCU FW is executing
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* CRDC[b0]: DP link success
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* CRDF[b0]: DP HPD
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* CRE5[b0]: Host reading EDID process is done
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*/
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while (!
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING)
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&& ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC,
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ASTDP_LINK_SUCCESS)
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&& ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF,
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ASTDP_HPD)
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&& ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
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ASTDP_HOST_EDID_READ_DONE_MASK))) {
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if (i++ > 10)
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goto err_astdp_edid_not_ready;
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mdelay(50);
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}
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
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(u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, 0x00);
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for (i = 0; i < 32; i++) {
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/*
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* CRE4[7:0]: Read-Pointer for
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* EDID (Unit: 4bytes); valid range: 0~64
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*/
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4,
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ASTDP_AND_CLEAR_MASK, (u8) i);
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j = 0;
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/*
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* CRD7[b0]: valid flag for EDID
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* CRD6[b0]: mirror read pointer for EDID
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*/
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while ((ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD7,
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ASTDP_EDID_VALID_FLAG_MASK) !=
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0x01)
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||
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xD6,
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ASTDP_EDID_READ_POINTER_MASK) != i)) {
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/*
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* Delay are getting longer with each retry.
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* 1. The Delays are often 2 loops when
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* users request "Display Settings" of
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* right-click of mouse.
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* 2. The Delays are often longer a lot when
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* system resume from S3/S4.
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*/
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mdelay(j + 1);
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if (!
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xD1,
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ASTDP_MCU_FW_EXECUTING)
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&& ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT,
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0xDF, ASTDP_HPD))) {
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goto err_astdp_jump_out_loop_of_edid;
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}
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j++;
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if (j > 200)
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goto err_astdp_jump_out_loop_of_edid;
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}
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*(ediddata) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT,
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0xD8,
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ASTDP_EDID_READ_DATA_MASK);
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*(ediddata + 1) =
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ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD9,
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ASTDP_EDID_READ_DATA_MASK);
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*(ediddata + 2) =
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ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDA,
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ASTDP_EDID_READ_DATA_MASK);
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*(ediddata + 3) =
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ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDB,
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ASTDP_EDID_READ_DATA_MASK);
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if (i == 31) {
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/*
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* For 128-bytes EDID_1.3,
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* 1. Add the value of Bytes-126 to Bytes-127.
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* The Bytes-127 is Checksum. Sum of all 128bytes
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* should equal 0 (mod 256).
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* 2. Modify Bytes-126 to be 0.
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* The Bytes-126 indicates the Number of extensions
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* to follow. 0 represents noextensions.
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*/
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*(ediddata + 3) = *(ediddata + 3) + *(ediddata + 2);
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*(ediddata + 2) = 0;
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}
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ediddata += 4;
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}
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
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(u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
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ASTDP_HOST_EDID_READ_DONE);
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return 0;
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err_astdp_jump_out_loop_of_edid:
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
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(u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
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ASTDP_HOST_EDID_READ_DONE);
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return (~(j + 256) + 1);
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err_astdp_edid_not_ready:
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if (!
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING)))
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return (~0xD1 + 1);
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if (!
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS)))
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return (~0xDC + 1);
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if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)))
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return (~0xDF + 1);
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if (!
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(ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xE5, ASTDP_HOST_EDID_READ_DONE_MASK)))
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return (~0xE5 + 1);
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return 0;
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}
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/*
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* Launch Aspeed DP
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*/
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void ast_dp_launch(struct drm_device *dev, u8 bPower)
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{
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u32 i = 0, j = 0, WaitCount = 1;
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u8 bDPTX = 0;
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u8 bDPExecute = 1;
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struct ast_private *ast = to_ast_private(dev);
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// S3 come back, need more time to wait BMC ready.
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if (bPower)
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WaitCount = 300;
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// Wait total count by different condition.
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for (j = 0; j < WaitCount; j++) {
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bDPTX =
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ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1,
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TX_TYPE_MASK);
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if (bDPTX)
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break;
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msleep(100);
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}
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// 0xE : ASTDP with DPMCU FW handling
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if (bDPTX == ASTDP_DPMCU_TX) {
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// Wait one second then timeout.
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i = 0;
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while (ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xD1,
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COPROCESSOR_LAUNCH) != COPROCESSOR_LAUNCH) {
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i++;
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// wait 100 ms
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msleep(100);
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if (i >= 10) {
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// DP would not be ready.
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bDPExecute = 0;
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break;
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}
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}
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if (bDPExecute)
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ast->tx_chip_type = AST_TX_ASTDP;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5,
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(u8) ~ASTDP_HOST_EDID_READ_DONE_MASK,
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ASTDP_HOST_EDID_READ_DONE);
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} else
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ast->tx_chip_type = AST_TX_NONE;
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}
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void ast_dp_power_on_off(struct drm_device *dev, bool on)
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{
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struct ast_private *ast = to_ast_private(dev);
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// Read and Turn off DP PHY sleep
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u8 bE3 =
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ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3,
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AST_DP_VIDEO_ENABLE);
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// Turn on DP PHY sleep
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if (!on)
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bE3 |= AST_DP_PHY_SLEEP;
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// DP Power on/off
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3,
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(u8) ~AST_DP_PHY_SLEEP, bE3);
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}
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void ast_dp_set_on_off(struct drm_device *dev, bool on)
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{
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struct ast_private *ast = to_ast_private(dev);
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u8 video_on_off = on;
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// Video On/Off
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3,
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(u8) ~AST_DP_VIDEO_ENABLE, on);
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// If DP plug in and link successful then check video on / off status
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if (ast_get_index_reg_mask
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(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS)
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&& ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)) {
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video_on_off <<= 4;
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while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF,
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ASTDP_MIRROR_VIDEO_ENABLE) !=
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video_on_off) {
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// wait 1 ms
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mdelay(1);
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}
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}
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}
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void ast_dp_set_mode(struct drm_crtc *crtc,
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struct ast_vbios_mode_info *vbios_mode)
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{
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struct ast_private *ast = to_ast_private(crtc->dev);
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u32 ulRefreshRateIndex;
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u8 ModeIdx;
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ulRefreshRateIndex = vbios_mode->enh_table->refresh_rate_index - 1;
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switch (crtc->mode.crtc_hdisplay) {
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case 320:
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ModeIdx = ASTDP_320x240_60;
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break;
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case 400:
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ModeIdx = ASTDP_400x300_60;
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break;
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case 512:
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ModeIdx = ASTDP_512x384_60;
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break;
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case 640:
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ModeIdx = (ASTDP_640x480_60 + (u8) ulRefreshRateIndex);
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break;
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case 800:
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ModeIdx = (ASTDP_800x600_56 + (u8) ulRefreshRateIndex);
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break;
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case 1024:
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ModeIdx = (ASTDP_1024x768_60 + (u8) ulRefreshRateIndex);
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break;
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case 1152:
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ModeIdx = ASTDP_1152x864_75;
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break;
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case 1280:
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if (crtc->mode.crtc_vdisplay == 800)
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ModeIdx =
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(ASTDP_1280x800_60_RB - (u8) ulRefreshRateIndex);
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else // 1024
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ModeIdx =
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(ASTDP_1280x1024_60 + (u8) ulRefreshRateIndex);
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break;
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case 1360:
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case 1366:
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ModeIdx = ASTDP_1366x768_60;
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break;
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case 1440:
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ModeIdx = (ASTDP_1440x900_60_RB - (u8) ulRefreshRateIndex);
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break;
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case 1600:
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if (crtc->mode.crtc_vdisplay == 900)
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ModeIdx =
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(ASTDP_1600x900_60_RB - (u8) ulRefreshRateIndex);
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else //1200
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ModeIdx = ASTDP_1600x1200_60;
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break;
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case 1680:
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ModeIdx = (ASTDP_1680x1050_60_RB - (u8) ulRefreshRateIndex);
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break;
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case 1920:
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if (crtc->mode.crtc_vdisplay == 1080)
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ModeIdx = ASTDP_1920x1080_60;
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else //1200
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ModeIdx = ASTDP_1920x1200_60;
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break;
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default:
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return;
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}
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/*
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* CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
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* CRE1[7:0]: MISC1 (default: 0x00)
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* CRE2[7:0]: video format index (0x00 ~0x20 or 0x40 ~0x50)
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*/
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0,
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ASTDP_AND_CLEAR_MASK, ASTDP_MISC0_24bpp);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1,
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ASTDP_AND_CLEAR_MASK, ASTDP_MISC1);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2,
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ASTDP_AND_CLEAR_MASK, ModeIdx);
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}
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