250 lines
6.1 KiB
ArmAsm
250 lines
6.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/unicore32/kernel/head.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/ptrace.h>
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#include <generated/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/hwdef-copro.h>
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#include <asm/pgtable-hwdef.h>
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#if (PHYS_OFFSET & 0x003fffff)
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#error "PHYS_OFFSET must be at an even 4MiB boundary!"
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#endif
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + KERNEL_IMAGE_START)
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#define KERNEL_RAM_PADDR (PHYS_OFFSET + KERNEL_IMAGE_START)
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#define KERNEL_PGD_PADDR (KERNEL_RAM_PADDR - 0x1000)
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#define KERNEL_PGD_VADDR (KERNEL_RAM_VADDR - 0x1000)
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#define KERNEL_START KERNEL_RAM_VADDR
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#define KERNEL_END _end
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/*
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* swapper_pg_dir is the virtual address of the initial page table.
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* We place the page tables 4K below KERNEL_RAM_VADDR. Therefore, we must
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* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
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* the least significant 16 bits to be 0x8000, but we could probably
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* relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x1000.
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*/
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#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
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#error KERNEL_RAM_VADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x1000
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*/
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__HEAD
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ENTRY(stext)
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@ set asr
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mov r0, #PRIV_MODE @ ensure priv mode
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or r0, #PSR_R_BIT | PSR_I_BIT @ disable irqs
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mov.a asr, r0
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@ process identify
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movc r0, p0.c0, #0 @ cpuid
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movl r1, 0xff00ffff @ mask
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movl r2, 0x4d000863 @ value
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and r0, r1, r0
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cxor.a r0, r2
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bne __error_p @ invalid processor id
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/*
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* Clear the 4K level 1 swapper page table
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*/
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movl r0, #KERNEL_PGD_PADDR @ page table address
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mov r1, #0
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add r2, r0, #0x1000
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101: stw.w r1, [r0]+, #4
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stw.w r1, [r0]+, #4
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stw.w r1, [r0]+, #4
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stw.w r1, [r0]+, #4
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cxor.a r0, r2
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bne 101b
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movl r4, #KERNEL_PGD_PADDR @ page table address
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mov r7, #PMD_TYPE_SECT | PMD_PRESENT @ page size: section
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or r7, r7, #PMD_SECT_CACHEABLE @ cacheable
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or r7, r7, #PMD_SECT_READ | PMD_SECT_WRITE | PMD_SECT_EXEC
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/*
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* Create identity mapping for first 4MB of kernel to
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* cater for the MMU enable. This identity mapping
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* will be removed by paging_init(). We use our current program
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* counter to determine corresponding section base address.
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*/
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mov r6, pc
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mov r6, r6 >> #22 @ start of kernel section
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or r1, r7, r6 << #22 @ flags + kernel base
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stw r1, [r4+], r6 << #2 @ identity mapping
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/*
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* Now setup the pagetables for our kernel direct
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* mapped region.
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*/
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add r0, r4, #(KERNEL_START & 0xff000000) >> 20
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stw.w r1, [r0+], #(KERNEL_START & 0x00c00000) >> 20
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movl r6, #(KERNEL_END - 1)
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add r0, r0, #4
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add r6, r4, r6 >> #20
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102: csub.a r0, r6
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add r1, r1, #1 << 22
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bua 103f
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stw.w r1, [r0]+, #4
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b 102b
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103:
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/*
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* Then map first 4MB of ram in case it contains our boot params.
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*/
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add r0, r4, #PAGE_OFFSET >> 20
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or r6, r7, #(PHYS_OFFSET & 0xffc00000)
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stw r6, [r0]
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ldw r15, __switch_data @ address to jump to after
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/*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on.
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*/
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mov r0, #0
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movc p0.c5, r0, #28 @ cache invalidate all
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nop8
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movc p0.c6, r0, #6 @ TLB invalidate all
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nop8
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/*
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* ..V. .... ..TB IDAM
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* ..1. .... ..01 1111
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*/
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movl r0, #0x201f @ control register setting
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/*
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* Setup common bits before finally enabling the MMU. Essentially
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* this is just loading the page table pointer and domain access
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* registers.
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*/
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#ifndef CONFIG_ALIGNMENT_TRAP
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andn r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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andn r0, r0, #CR_D
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#endif
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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andn r0, r0, #CR_B
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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andn r0, r0, #CR_I
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#endif
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movc p0.c2, r4, #0 @ set pgd
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b __turn_mmu_on
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ENDPROC(stext)
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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*
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* r0 = cp#0 control register
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* r15 = *virtual* address to jump to upon completion
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*/
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.align 5
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__turn_mmu_on:
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mov r0, r0
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movc p0.c1, r0, #0 @ write control reg
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nop @ fetch inst by phys addr
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mov pc, r15
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nop8 @ fetch inst by phys addr
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ENDPROC(__turn_mmu_on)
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r9 = cpuid
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* r10 = procinfo
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*
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* Returns:
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* r0, r3, r6, r7 corrupted
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* r4 = physical page table address
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*/
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.ltorg
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.align 2
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.type __switch_data, %object
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__switch_data:
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.long __mmap_switched
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.long __bss_start @ r6
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.long _end @ r7
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.long cr_alignment @ r8
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.long init_thread_union + THREAD_START_SP @ sp
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/*
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* The following fragment of code is executed with the MMU on in MMU mode,
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* and uses absolute addresses; this is not position independent.
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*
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* r0 = cp#0 control register
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*/
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__mmap_switched:
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adr r3, __switch_data + 4
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ldm.w (r6, r7, r8), [r3]+
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ldw sp, [r3]
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mov fp, #0 @ Clear BSS (and zero fp)
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203: csub.a r6, r7
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bea 204f
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stw.w fp, [r6]+,#4
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b 203b
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204:
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andn r1, r0, #CR_A @ Clear 'A' bit
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stm (r0, r1), [r8]+ @ Save control register values
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b start_kernel
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ENDPROC(__mmap_switched)
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/*
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* Exception handling. Something went wrong and we can't proceed. We
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* ought to tell the user, but since we don't have any guarantee that
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* we're even running on the right architecture, we do virtually nothing.
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*
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* If CONFIG_DEBUG_LL is set we try to print out something about the error
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* and hope for the best (useful if bootloader fails to pass a proper
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* machine ID for example).
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*/
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__error_p:
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#ifdef CONFIG_DEBUG_LL
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adr r0, str_p1
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b.l printascii
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mov r0, r9
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b.l printhex8
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adr r0, str_p2
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b.l printascii
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901: nop8
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b 901b
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str_p1: .asciz "\nError: unrecognized processor variant (0x"
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str_p2: .asciz ").\n"
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.align
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#endif
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ENDPROC(__error_p)
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