159 lines
3.8 KiB
C
159 lines
3.8 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef DEBUG_H
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#define DEBUG_H
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enum ATH_DEBUG {
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ATH_DBG_RESET = 0x00000001,
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ATH_DBG_QUEUE = 0x00000002,
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ATH_DBG_EEPROM = 0x00000004,
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ATH_DBG_CALIBRATE = 0x00000008,
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ATH_DBG_INTERRUPT = 0x00000010,
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ATH_DBG_REGULATORY = 0x00000020,
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ATH_DBG_ANI = 0x00000040,
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ATH_DBG_XMIT = 0x00000080,
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ATH_DBG_BEACON = 0x00000100,
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ATH_DBG_CONFIG = 0x00000200,
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ATH_DBG_FATAL = 0x00000400,
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ATH_DBG_PS = 0x00000800,
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ATH_DBG_ANY = 0xffffffff
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};
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#define DBG_DEFAULT (ATH_DBG_FATAL)
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#ifdef CONFIG_ATH9K_DEBUG
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/**
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* struct ath_interrupt_stats - Contains statistics about interrupts
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* @total: Total no. of interrupts generated so far
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* @rxok: RX with no errors
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* @rxeol: RX with no more RXDESC available
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* @rxorn: RX FIFO overrun
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* @txok: TX completed at the requested rate
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* @txurn: TX FIFO underrun
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* @mib: MIB regs reaching its threshold
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* @rxphyerr: RX with phy errors
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* @rx_keycache_miss: RX with key cache misses
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* @swba: Software Beacon Alert
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* @bmiss: Beacon Miss
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* @bnr: Beacon Not Ready
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* @cst: Carrier Sense TImeout
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* @gtt: Global TX Timeout
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* @tim: RX beacon TIM occurrence
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* @cabend: RX End of CAB traffic
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* @dtimsync: DTIM sync lossage
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* @dtim: RX Beacon with DTIM
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*/
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struct ath_interrupt_stats {
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u32 total;
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u32 rxok;
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u32 rxeol;
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u32 rxorn;
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u32 txok;
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u32 txeol;
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u32 txurn;
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u32 mib;
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u32 rxphyerr;
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u32 rx_keycache_miss;
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u32 swba;
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u32 bmiss;
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u32 bnr;
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u32 cst;
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u32 gtt;
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u32 tim;
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u32 cabend;
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u32 dtimsync;
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u32 dtim;
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};
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struct ath_rc_stats {
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u32 success;
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u32 retries;
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u32 xretries;
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u8 per;
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};
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struct ath_stats {
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struct ath_interrupt_stats istats;
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struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
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};
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struct ath9k_debug {
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int debug_mask;
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struct dentry *debugfs_phy;
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struct dentry *debugfs_debug;
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struct dentry *debugfs_dma;
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struct dentry *debugfs_interrupt;
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struct dentry *debugfs_rcstat;
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struct dentry *debugfs_wiphy;
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struct ath_stats stats;
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};
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void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
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int ath9k_init_debug(struct ath_softc *sc);
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void ath9k_exit_debug(struct ath_softc *sc);
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int ath9k_debug_create_root(void);
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void ath9k_debug_remove_root(void);
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void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
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void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb);
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void ath_debug_stat_retries(struct ath_softc *sc, int rix,
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int xretries, int retries, u8 per);
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#else
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static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
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const char *fmt, ...)
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{
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}
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static inline int ath9k_init_debug(struct ath_softc *sc)
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{
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return 0;
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}
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static inline void ath9k_exit_debug(struct ath_softc *sc)
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{
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}
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static inline int ath9k_debug_create_root(void)
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{
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return 0;
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}
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static inline void ath9k_debug_remove_root(void)
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{
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}
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static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
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enum ath9k_int status)
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{
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}
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static inline void ath_debug_stat_rc(struct ath_softc *sc,
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struct sk_buff *skb)
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{
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}
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static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
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int xretries, int retries, u8 per)
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{
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}
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#endif /* CONFIG_ATH9K_DEBUG */
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#endif /* DEBUG_H */
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