607 lines
17 KiB
C
607 lines
17 KiB
C
/*******************************************************************************
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Intel PRO/10GbE Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include "ixgb_hw.h"
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#include "ixgb_ee.h"
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/* Local prototypes */
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static u16 ixgb_shift_in_bits(struct ixgb_hw *hw);
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static void ixgb_shift_out_bits(struct ixgb_hw *hw,
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u16 data,
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u16 count);
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static void ixgb_standby_eeprom(struct ixgb_hw *hw);
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static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw);
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static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
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/******************************************************************************
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* Raises the EEPROM's clock input.
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*
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* hw - Struct containing variables accessed by shared code
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* eecd_reg - EECD's current value
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*****************************************************************************/
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static void
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ixgb_raise_clock(struct ixgb_hw *hw,
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u32 *eecd_reg)
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{
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/* Raise the clock input to the EEPROM (by setting the SK bit), and then
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* wait 50 microseconds.
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*/
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*eecd_reg = *eecd_reg | IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, *eecd_reg);
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udelay(50);
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return;
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}
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/******************************************************************************
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* Lowers the EEPROM's clock input.
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*
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* hw - Struct containing variables accessed by shared code
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* eecd_reg - EECD's current value
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*****************************************************************************/
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static void
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ixgb_lower_clock(struct ixgb_hw *hw,
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u32 *eecd_reg)
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{
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/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
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* wait 50 microseconds.
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*/
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*eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, *eecd_reg);
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udelay(50);
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return;
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}
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/******************************************************************************
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* Shift data bits out to the EEPROM.
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*
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* hw - Struct containing variables accessed by shared code
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* data - data to send to the EEPROM
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* count - number of bits to shift out
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*****************************************************************************/
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static void
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ixgb_shift_out_bits(struct ixgb_hw *hw,
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u16 data,
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u16 count)
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{
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u32 eecd_reg;
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u32 mask;
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/* We need to shift "count" bits out to the EEPROM. So, value in the
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* "data" parameter will be shifted out to the EEPROM one bit at a time.
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* In order to do this, "data" must be broken down into bits.
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*/
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mask = 0x01 << (count - 1);
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eecd_reg = IXGB_READ_REG(hw, EECD);
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eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
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do {
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/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
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* and then raising and then lowering the clock (the SK bit controls
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* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
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* by setting "DI" to "0" and then raising and then lowering the clock.
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*/
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eecd_reg &= ~IXGB_EECD_DI;
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if (data & mask)
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eecd_reg |= IXGB_EECD_DI;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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ixgb_raise_clock(hw, &eecd_reg);
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ixgb_lower_clock(hw, &eecd_reg);
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mask = mask >> 1;
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} while (mask);
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/* We leave the "DI" bit set to "0" when we leave this routine. */
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eecd_reg &= ~IXGB_EECD_DI;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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return;
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}
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/******************************************************************************
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* Shift data bits in from the EEPROM
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*
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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static u16
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ixgb_shift_in_bits(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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u32 i;
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u16 data;
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/* In order to read a register from the EEPROM, we need to shift 16 bits
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* in from the EEPROM. Bits are "shifted in" by raising the clock input to
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* the EEPROM (setting the SK bit), and then reading the value of the "DO"
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* bit. During this "shifting in" process the "DI" bit should always be
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* clear..
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*/
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eecd_reg = IXGB_READ_REG(hw, EECD);
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eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
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data = 0;
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for (i = 0; i < 16; i++) {
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data = data << 1;
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ixgb_raise_clock(hw, &eecd_reg);
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eecd_reg = IXGB_READ_REG(hw, EECD);
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eecd_reg &= ~(IXGB_EECD_DI);
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if (eecd_reg & IXGB_EECD_DO)
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data |= 1;
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ixgb_lower_clock(hw, &eecd_reg);
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}
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return data;
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}
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/******************************************************************************
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* Prepares EEPROM for access
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
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* function should be called before issuing a command to the EEPROM.
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*****************************************************************************/
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static void
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ixgb_setup_eeprom(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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eecd_reg = IXGB_READ_REG(hw, EECD);
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/* Clear SK and DI */
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eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI);
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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/* Set CS */
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eecd_reg |= IXGB_EECD_CS;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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return;
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}
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/******************************************************************************
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* Returns EEPROM to a "standby" state
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*
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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static void
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ixgb_standby_eeprom(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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eecd_reg = IXGB_READ_REG(hw, EECD);
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/* Deselect EEPROM */
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eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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/* Clock high */
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eecd_reg |= IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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/* Select EEPROM */
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eecd_reg |= IXGB_EECD_CS;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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/* Clock low */
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eecd_reg &= ~IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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return;
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}
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/******************************************************************************
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* Raises then lowers the EEPROM's clock pin
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*
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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static void
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ixgb_clock_eeprom(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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eecd_reg = IXGB_READ_REG(hw, EECD);
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/* Rising edge of clock */
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eecd_reg |= IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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/* Falling edge of clock */
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eecd_reg &= ~IXGB_EECD_SK;
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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udelay(50);
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return;
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}
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/******************************************************************************
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* Terminates a command by lowering the EEPROM's chip select pin
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*
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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static void
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ixgb_cleanup_eeprom(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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eecd_reg = IXGB_READ_REG(hw, EECD);
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eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI);
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IXGB_WRITE_REG(hw, EECD, eecd_reg);
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ixgb_clock_eeprom(hw);
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return;
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}
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/******************************************************************************
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* Waits for the EEPROM to finish the current command.
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*
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* hw - Struct containing variables accessed by shared code
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*
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* The command is done when the EEPROM's data out pin goes high.
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*
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* Returns:
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* true: EEPROM data pin is high before timeout.
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* false: Time expired.
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*****************************************************************************/
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static bool
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ixgb_wait_eeprom_command(struct ixgb_hw *hw)
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{
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u32 eecd_reg;
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u32 i;
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/* Toggle the CS line. This in effect tells to EEPROM to actually execute
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* the command in question.
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*/
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ixgb_standby_eeprom(hw);
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/* Now read DO repeatedly until is high (equal to '1'). The EEPROM will
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* signal that the command has been completed by raising the DO signal.
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* If DO does not go high in 10 milliseconds, then error out.
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*/
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for (i = 0; i < 200; i++) {
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eecd_reg = IXGB_READ_REG(hw, EECD);
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if (eecd_reg & IXGB_EECD_DO)
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return (true);
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udelay(50);
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}
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ASSERT(0);
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return (false);
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}
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/******************************************************************************
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* Verifies that the EEPROM has a valid checksum
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Reads the first 64 16 bit words of the EEPROM and sums the values read.
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* If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
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* valid.
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*
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* Returns:
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* true: Checksum is valid
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* false: Checksum is not valid.
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*****************************************************************************/
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bool
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ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
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{
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u16 checksum = 0;
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u16 i;
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for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
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checksum += ixgb_read_eeprom(hw, i);
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if (checksum == (u16) EEPROM_SUM)
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return (true);
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else
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return (false);
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}
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/******************************************************************************
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* Calculates the EEPROM checksum and writes it to the EEPROM
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
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* Writes the difference to word offset 63 of the EEPROM.
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*****************************************************************************/
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void
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ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
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{
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u16 checksum = 0;
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u16 i;
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for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
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checksum += ixgb_read_eeprom(hw, i);
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checksum = (u16) EEPROM_SUM - checksum;
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ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
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return;
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}
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/******************************************************************************
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* Writes a 16 bit word to a given offset in the EEPROM.
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*
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* hw - Struct containing variables accessed by shared code
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* reg - offset within the EEPROM to be written to
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* data - 16 bit word to be written to the EEPROM
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*
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* If ixgb_update_eeprom_checksum is not called after this function, the
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* EEPROM will most likely contain an invalid checksum.
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*
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*****************************************************************************/
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void
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ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data)
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{
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struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
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/* Prepare the EEPROM for writing */
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ixgb_setup_eeprom(hw);
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/* Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode
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* plus 4-bit dummy). This puts the EEPROM into write/erase mode.
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*/
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ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
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ixgb_shift_out_bits(hw, 0, 4);
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/* Prepare the EEPROM */
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ixgb_standby_eeprom(hw);
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/* Send the Write command (3-bit opcode + 6-bit addr) */
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ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
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ixgb_shift_out_bits(hw, offset, 6);
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/* Send the data */
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ixgb_shift_out_bits(hw, data, 16);
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ixgb_wait_eeprom_command(hw);
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/* Recover from write */
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ixgb_standby_eeprom(hw);
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/* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit
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* opcode plus 4-bit dummy). This takes the EEPROM out of write/erase
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* mode.
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*/
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ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
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ixgb_shift_out_bits(hw, 0, 4);
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/* Done with writing */
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ixgb_cleanup_eeprom(hw);
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/* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
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ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
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return;
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}
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/******************************************************************************
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* Reads a 16 bit word from the EEPROM.
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*
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* hw - Struct containing variables accessed by shared code
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* offset - offset of 16 bit word in the EEPROM to read
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*
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* Returns:
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* The 16-bit value read from the eeprom
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*****************************************************************************/
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u16
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ixgb_read_eeprom(struct ixgb_hw *hw,
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u16 offset)
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{
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u16 data;
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/* Prepare the EEPROM for reading */
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ixgb_setup_eeprom(hw);
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/* Send the READ command (opcode + addr) */
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ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
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/*
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* We have a 64 word EEPROM, there are 6 address bits
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*/
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ixgb_shift_out_bits(hw, offset, 6);
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/* Read the data */
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data = ixgb_shift_in_bits(hw);
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/* End this read operation */
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ixgb_standby_eeprom(hw);
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return (data);
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}
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/******************************************************************************
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* Reads eeprom and stores data in shared structure.
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* Validates eeprom checksum and eeprom signature.
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Returns:
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* true: if eeprom read is successful
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* false: otherwise.
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*****************************************************************************/
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bool
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ixgb_get_eeprom_data(struct ixgb_hw *hw)
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{
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u16 i;
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u16 checksum = 0;
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struct ixgb_ee_map_type *ee_map;
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DEBUGFUNC("ixgb_get_eeprom_data");
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ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
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DEBUGOUT("ixgb_ee: Reading eeprom data\n");
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for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
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u16 ee_data;
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ee_data = ixgb_read_eeprom(hw, i);
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checksum += ee_data;
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hw->eeprom[i] = cpu_to_le16(ee_data);
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}
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if (checksum != (u16) EEPROM_SUM) {
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DEBUGOUT("ixgb_ee: Checksum invalid.\n");
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/* clear the init_ctrl_reg_1 to signify that the cache is
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* invalidated */
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ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
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return (false);
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}
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if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
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!= cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
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DEBUGOUT("ixgb_ee: Signature invalid.\n");
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return(false);
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}
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return(true);
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}
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/******************************************************************************
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* Local function to check if the eeprom signature is good
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* If the eeprom signature is good, calls ixgb)get_eeprom_data.
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Returns:
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* true: eeprom signature was good and the eeprom read was successful
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* false: otherwise.
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******************************************************************************/
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static bool
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ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
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{
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struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
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if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
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== cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
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return (true);
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} else {
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return ixgb_get_eeprom_data(hw);
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}
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}
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/******************************************************************************
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* return a word from the eeprom
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*
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* hw - Struct containing variables accessed by shared code
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* index - Offset of eeprom word
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*
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|
* Returns:
|
|
* Word at indexed offset in eeprom, if valid, 0 otherwise.
|
|
******************************************************************************/
|
|
__le16
|
|
ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index)
|
|
{
|
|
|
|
if ((index < IXGB_EEPROM_SIZE) &&
|
|
(ixgb_check_and_get_eeprom_data(hw) == true)) {
|
|
return(hw->eeprom[index]);
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* return the mac address from EEPROM
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise
|
|
*
|
|
* Returns: None.
|
|
******************************************************************************/
|
|
void
|
|
ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
|
|
u8 *mac_addr)
|
|
{
|
|
int i;
|
|
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
|
|
|
|
DEBUGFUNC("ixgb_get_ee_mac_addr");
|
|
|
|
if (ixgb_check_and_get_eeprom_data(hw) == true) {
|
|
for (i = 0; i < IXGB_ETH_LENGTH_OF_ADDRESS; i++) {
|
|
mac_addr[i] = ee_map->mac_addr[i];
|
|
DEBUGOUT2("mac(%d) = %.2X\n", i, mac_addr[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
* return the Printed Board Assembly number from EEPROM
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*
|
|
* Returns:
|
|
* PBA number if EEPROM contents are valid, 0 otherwise
|
|
******************************************************************************/
|
|
u32
|
|
ixgb_get_ee_pba_number(struct ixgb_hw *hw)
|
|
{
|
|
if (ixgb_check_and_get_eeprom_data(hw) == true)
|
|
return (le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
|
|
| (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16));
|
|
|
|
return(0);
|
|
}
|
|
|
|
|
|
/******************************************************************************
|
|
* return the Device Id from EEPROM
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*
|
|
* Returns:
|
|
* Device Id if EEPROM contents are valid, 0 otherwise
|
|
******************************************************************************/
|
|
u16
|
|
ixgb_get_ee_device_id(struct ixgb_hw *hw)
|
|
{
|
|
struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
|
|
|
|
if (ixgb_check_and_get_eeprom_data(hw) == true)
|
|
return (le16_to_cpu(ee_map->device_id));
|
|
|
|
return (0);
|
|
}
|
|
|