247 lines
8.0 KiB
C
247 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* sound/soc/rockchip/rockchip_i2s.h
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*
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* ALSA SoC Audio Layer - Rockchip I2S Controller driver
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*
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* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
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* Author: Jianqun xu <jay.xu@rock-chips.com>
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*/
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#ifndef _ROCKCHIP_IIS_H
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#define _ROCKCHIP_IIS_H
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/*
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* TXCR
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* transmit operation control register
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*/
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#define I2S_TXCR_RCNT_SHIFT 17
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#define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT)
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#define I2S_TXCR_CSR_SHIFT 15
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#define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT)
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#define I2S_TXCR_HWT BIT(14)
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#define I2S_TXCR_SJM_SHIFT 12
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#define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT)
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#define I2S_TXCR_FBM_SHIFT 11
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#define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT)
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#define I2S_TXCR_IBM_SHIFT 9
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#define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT)
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#define I2S_TXCR_PBM_SHIFT 7
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#define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT)
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#define I2S_TXCR_TFS_SHIFT 5
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#define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT)
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#define I2S_TXCR_VDW_SHIFT 0
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#define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT)
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#define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT)
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/*
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* RXCR
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* receive operation control register
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*/
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#define I2S_RXCR_CSR_SHIFT 15
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#define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT)
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#define I2S_RXCR_HWT BIT(14)
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#define I2S_RXCR_SJM_SHIFT 12
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#define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT)
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#define I2S_RXCR_FBM_SHIFT 11
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#define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT)
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#define I2S_RXCR_IBM_SHIFT 9
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#define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT)
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#define I2S_RXCR_PBM_SHIFT 7
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#define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT)
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#define I2S_RXCR_TFS_SHIFT 5
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#define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT)
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#define I2S_RXCR_VDW_SHIFT 0
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#define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT)
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#define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT)
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/*
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* CKR
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* clock generation register
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*/
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#define I2S_CKR_TRCM_SHIFT 28
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#define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT)
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#define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT)
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#define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT)
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#define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT)
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#define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT)
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#define I2S_CKR_MSS_SHIFT 27
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#define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT)
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#define I2S_CKR_CKP_SHIFT 26
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#define I2S_CKR_CKP_NEG (0 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_POS (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT)
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#define I2S_CKR_RLP_SHIFT 25
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#define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_RLP_OPPSITE (1 << I2S_CKR_RLP_SHIFT)
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#define I2S_CKR_TLP_SHIFT 24
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#define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_TLP_OPPSITE (1 << I2S_CKR_TLP_SHIFT)
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#define I2S_CKR_MDIV_SHIFT 16
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#define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT)
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#define I2S_CKR_RSD_SHIFT 8
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#define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT)
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#define I2S_CKR_TSD_SHIFT 0
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#define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT)
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#define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT)
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/*
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* FIFOLR
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* FIFO level register
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*/
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#define I2S_FIFOLR_RFL_SHIFT 24
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#define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT)
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#define I2S_FIFOLR_TFL3_SHIFT 18
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#define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT)
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#define I2S_FIFOLR_TFL2_SHIFT 12
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#define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT)
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#define I2S_FIFOLR_TFL1_SHIFT 6
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#define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT)
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#define I2S_FIFOLR_TFL0_SHIFT 0
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#define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT)
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/*
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* DMACR
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* DMA control register
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*/
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#define I2S_DMACR_RDE_SHIFT 24
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#define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT)
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#define I2S_DMACR_RDL_SHIFT 16
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#define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT)
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#define I2S_DMACR_TDE_SHIFT 8
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#define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT)
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#define I2S_DMACR_TDL_SHIFT 0
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#define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT)
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#define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT)
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/*
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* INTCR
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* interrupt control register
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*/
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#define I2S_INTCR_RFT_SHIFT 20
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#define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT)
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#define I2S_INTCR_RXOIC BIT(18)
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#define I2S_INTCR_RXOIE_SHIFT 17
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#define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT)
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#define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT)
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#define I2S_INTCR_RXFIE_SHIFT 16
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#define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT)
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#define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT)
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#define I2S_INTCR_TFT_SHIFT 4
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#define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT)
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#define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT)
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#define I2S_INTCR_TXUIC BIT(2)
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#define I2S_INTCR_TXUIE_SHIFT 1
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#define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT)
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#define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT)
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/*
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* INTSR
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* interrupt status register
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*/
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#define I2S_INTSR_TXEIE_SHIFT 0
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#define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT)
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#define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT)
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#define I2S_INTSR_RXOI_SHIFT 17
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#define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT)
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#define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT)
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#define I2S_INTSR_RXFI_SHIFT 16
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#define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT)
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#define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT)
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#define I2S_INTSR_TXUI_SHIFT 1
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#define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT)
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#define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT)
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#define I2S_INTSR_TXEI_SHIFT 0
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#define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT)
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#define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT)
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/*
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* XFER
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* Transfer start register
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*/
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#define I2S_XFER_RXS_SHIFT 1
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#define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT)
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#define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT)
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#define I2S_XFER_TXS_SHIFT 0
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#define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT)
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#define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT)
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/*
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* CLR
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* clear SCLK domain logic register
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*/
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#define I2S_CLR_RXC BIT(1)
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#define I2S_CLR_TXC BIT(0)
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/*
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* TXDR
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* Transimt FIFO data register, write only.
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*/
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#define I2S_TXDR_MASK (0xff)
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/*
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* RXDR
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* Receive FIFO data register, write only.
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*/
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#define I2S_RXDR_MASK (0xff)
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/* Clock divider id */
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enum {
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ROCKCHIP_DIV_MCLK = 0,
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ROCKCHIP_DIV_BCLK,
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};
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/* channel select */
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#define I2S_CSR_SHIFT 15
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#define I2S_CHN_2 (0 << I2S_CSR_SHIFT)
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#define I2S_CHN_4 (1 << I2S_CSR_SHIFT)
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#define I2S_CHN_6 (2 << I2S_CSR_SHIFT)
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#define I2S_CHN_8 (3 << I2S_CSR_SHIFT)
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/* I2S REGS */
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#define I2S_TXCR (0x0000)
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#define I2S_RXCR (0x0004)
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#define I2S_CKR (0x0008)
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#define I2S_FIFOLR (0x000c)
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#define I2S_DMACR (0x0010)
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#define I2S_INTCR (0x0014)
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#define I2S_INTSR (0x0018)
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#define I2S_XFER (0x001c)
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#define I2S_CLR (0x0020)
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#define I2S_TXDR (0x0024)
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#define I2S_RXDR (0x0028)
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/* io direction cfg register */
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#define I2S_IO_DIRECTION_MASK (7)
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#define I2S_IO_8CH_OUT_2CH_IN (0)
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#define I2S_IO_6CH_OUT_4CH_IN (4)
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#define I2S_IO_4CH_OUT_6CH_IN (6)
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#define I2S_IO_2CH_OUT_8CH_IN (7)
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#endif /* _ROCKCHIP_IIS_H */
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