201 lines
4.2 KiB
C
201 lines
4.2 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2018 Intel Corporation
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*/
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#include "gt/intel_gt.h"
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#include "gem/selftests/igt_gem_utils.h"
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#include "igt_spinner.h"
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int igt_spinner_init(struct igt_spinner *spin, struct intel_gt *gt)
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{
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unsigned int mode;
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void *vaddr;
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int err;
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GEM_BUG_ON(INTEL_GEN(gt->i915) < 8);
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memset(spin, 0, sizeof(*spin));
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spin->gt = gt;
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spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
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if (IS_ERR(spin->hws)) {
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err = PTR_ERR(spin->hws);
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goto err;
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}
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spin->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
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if (IS_ERR(spin->obj)) {
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err = PTR_ERR(spin->obj);
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goto err_hws;
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}
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i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC);
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vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_obj;
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}
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spin->seqno = memset(vaddr, 0xff, PAGE_SIZE);
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mode = i915_coherent_map_type(gt->i915);
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vaddr = i915_gem_object_pin_map(spin->obj, mode);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_unpin_hws;
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}
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spin->batch = vaddr;
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return 0;
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err_unpin_hws:
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i915_gem_object_unpin_map(spin->hws);
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err_obj:
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i915_gem_object_put(spin->obj);
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err_hws:
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i915_gem_object_put(spin->hws);
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err:
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return err;
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}
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static unsigned int seqno_offset(u64 fence)
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{
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return offset_in_page(sizeof(u32) * fence);
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}
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static u64 hws_address(const struct i915_vma *hws,
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const struct i915_request *rq)
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{
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return hws->node.start + seqno_offset(rq->fence.context);
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}
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static int move_to_active(struct i915_vma *vma,
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struct i915_request *rq,
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unsigned int flags)
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{
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int err;
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i915_vma_lock(vma);
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err = i915_vma_move_to_active(vma, rq, flags);
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i915_vma_unlock(vma);
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return err;
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}
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struct i915_request *
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igt_spinner_create_request(struct igt_spinner *spin,
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struct intel_context *ce,
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u32 arbitration_command)
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{
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struct intel_engine_cs *engine = ce->engine;
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struct i915_request *rq = NULL;
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struct i915_vma *hws, *vma;
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u32 *batch;
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int err;
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GEM_BUG_ON(spin->gt != ce->vm->gt);
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vma = i915_vma_instance(spin->obj, ce->vm, NULL);
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if (IS_ERR(vma))
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return ERR_CAST(vma);
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hws = i915_vma_instance(spin->hws, ce->vm, NULL);
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if (IS_ERR(hws))
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return ERR_CAST(hws);
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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return ERR_PTR(err);
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err = i915_vma_pin(hws, 0, 0, PIN_USER);
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if (err)
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goto unpin_vma;
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto unpin_hws;
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}
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err = move_to_active(vma, rq, 0);
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if (err)
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goto cancel_rq;
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err = move_to_active(hws, rq, 0);
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if (err)
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goto cancel_rq;
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batch = spin->batch;
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = upper_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = arbitration_command;
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*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
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*batch++ = lower_32_bits(vma->node.start);
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*batch++ = upper_32_bits(vma->node.start);
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*batch++ = MI_BATCH_BUFFER_END; /* not reached */
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intel_gt_chipset_flush(engine->gt);
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if (engine->emit_init_breadcrumb &&
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rq->timeline->has_initial_breadcrumb) {
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err = engine->emit_init_breadcrumb(rq);
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if (err)
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goto cancel_rq;
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}
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err = engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, 0);
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cancel_rq:
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if (err) {
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i915_request_skip(rq, err);
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i915_request_add(rq);
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}
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unpin_hws:
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i915_vma_unpin(hws);
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unpin_vma:
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i915_vma_unpin(vma);
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return err ? ERR_PTR(err) : rq;
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}
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static u32
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hws_seqno(const struct igt_spinner *spin, const struct i915_request *rq)
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{
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u32 *seqno = spin->seqno + seqno_offset(rq->fence.context);
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return READ_ONCE(*seqno);
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}
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void igt_spinner_end(struct igt_spinner *spin)
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{
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*spin->batch = MI_BATCH_BUFFER_END;
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intel_gt_chipset_flush(spin->gt);
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}
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void igt_spinner_fini(struct igt_spinner *spin)
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{
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igt_spinner_end(spin);
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i915_gem_object_unpin_map(spin->obj);
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i915_gem_object_put(spin->obj);
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i915_gem_object_unpin_map(spin->hws);
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i915_gem_object_put(spin->hws);
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}
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bool igt_wait_for_spinner(struct igt_spinner *spin, struct i915_request *rq)
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{
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return !(wait_for_us(i915_seqno_passed(hws_seqno(spin, rq),
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rq->fence.seqno),
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10) &&
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wait_for(i915_seqno_passed(hws_seqno(spin, rq),
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rq->fence.seqno),
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1000));
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}
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