613 lines
15 KiB
C
613 lines
15 KiB
C
/*
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* ADS1015 - Texas Instruments Analog-to-Digital Converter
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*
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* Copyright (c) 2016, Intel Corporation.
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*
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* This file is subject to the terms and conditions of version 2 of
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* the GNU General Public License. See the file COPYING in the main
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* directory of this archive for more details.
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*
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* IIO driver for ADS1015 ADC 7-bit I2C slave address:
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* * 0x48 - ADDR connected to Ground
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* * 0x49 - ADDR connected to Vdd
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* * 0x4A - ADDR connected to SDA
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* * 0x4B - ADDR connected to SCL
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/i2c/ads1015.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/types.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#define ADS1015_DRV_NAME "ads1015"
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#define ADS1015_CONV_REG 0x00
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#define ADS1015_CFG_REG 0x01
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#define ADS1015_CFG_DR_SHIFT 5
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#define ADS1015_CFG_MOD_SHIFT 8
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#define ADS1015_CFG_PGA_SHIFT 9
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#define ADS1015_CFG_MUX_SHIFT 12
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#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
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#define ADS1015_CFG_MOD_MASK BIT(8)
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#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
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#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
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/* device operating modes */
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#define ADS1015_CONTINUOUS 0
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#define ADS1015_SINGLESHOT 1
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#define ADS1015_SLEEP_DELAY_MS 2000
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#define ADS1015_DEFAULT_PGA 2
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#define ADS1015_DEFAULT_DATA_RATE 4
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#define ADS1015_DEFAULT_CHAN 0
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enum ads1015_channels {
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ADS1015_AIN0_AIN1 = 0,
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ADS1015_AIN0_AIN3,
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ADS1015_AIN1_AIN3,
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ADS1015_AIN2_AIN3,
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ADS1015_AIN0,
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ADS1015_AIN1,
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ADS1015_AIN2,
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ADS1015_AIN3,
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ADS1015_TIMESTAMP,
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};
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static const unsigned int ads1015_data_rate[] = {
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128, 250, 490, 920, 1600, 2400, 3300, 3300
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};
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static const struct {
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int scale;
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int uscale;
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} ads1015_scale[] = {
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{3, 0},
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{2, 0},
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{1, 0},
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{0, 500000},
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{0, 250000},
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{0, 125000},
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{0, 125000},
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{0, 125000},
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};
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#define ADS1015_V_CHAN(_chan, _addr) { \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.address = _addr, \
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.channel = _chan, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.scan_index = _addr, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 12, \
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.storagebits = 16, \
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.shift = 4, \
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.endianness = IIO_CPU, \
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}, \
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}
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#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
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.type = IIO_VOLTAGE, \
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.differential = 1, \
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.indexed = 1, \
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.address = _addr, \
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.channel = _chan, \
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.channel2 = _chan2, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE) | \
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BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.scan_index = _addr, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 12, \
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.storagebits = 16, \
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.shift = 4, \
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.endianness = IIO_CPU, \
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}, \
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}
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struct ads1015_data {
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struct regmap *regmap;
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/*
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* Protects ADC ops, e.g: concurrent sysfs/buffered
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* data reads, configuration updates
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*/
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struct mutex lock;
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struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
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};
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static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
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{
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return (reg == ADS1015_CFG_REG);
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}
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static const struct regmap_config ads1015_regmap_config = {
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.reg_bits = 8,
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.val_bits = 16,
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.max_register = ADS1015_CFG_REG,
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.writeable_reg = ads1015_is_writeable_reg,
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};
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static const struct iio_chan_spec ads1015_channels[] = {
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ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
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ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
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ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
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ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
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ADS1015_V_CHAN(0, ADS1015_AIN0),
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ADS1015_V_CHAN(1, ADS1015_AIN1),
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ADS1015_V_CHAN(2, ADS1015_AIN2),
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ADS1015_V_CHAN(3, ADS1015_AIN3),
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IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
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};
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static int ads1015_set_power_state(struct ads1015_data *data, bool on)
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{
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int ret;
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struct device *dev = regmap_get_device(data->regmap);
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if (on) {
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ret = pm_runtime_get_sync(dev);
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if (ret < 0)
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pm_runtime_put_noidle(dev);
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} else {
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pm_runtime_mark_last_busy(dev);
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ret = pm_runtime_put_autosuspend(dev);
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}
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return ret;
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}
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static
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int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
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{
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int ret, pga, dr, conv_time;
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bool change;
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if (chan < 0 || chan >= ADS1015_CHANNELS)
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return -EINVAL;
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pga = data->channel_data[chan].pga;
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dr = data->channel_data[chan].data_rate;
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ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
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ADS1015_CFG_MUX_MASK |
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ADS1015_CFG_PGA_MASK,
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chan << ADS1015_CFG_MUX_SHIFT |
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pga << ADS1015_CFG_PGA_SHIFT,
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&change);
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if (ret < 0)
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return ret;
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if (change) {
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conv_time = DIV_ROUND_UP(USEC_PER_SEC, ads1015_data_rate[dr]);
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usleep_range(conv_time, conv_time + 1);
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}
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return regmap_read(data->regmap, ADS1015_CONV_REG, val);
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}
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static irqreturn_t ads1015_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio_dev = pf->indio_dev;
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struct ads1015_data *data = iio_priv(indio_dev);
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s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
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int chan, ret, res;
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memset(buf, 0, sizeof(buf));
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mutex_lock(&data->lock);
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chan = find_first_bit(indio_dev->active_scan_mask,
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indio_dev->masklength);
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ret = ads1015_get_adc_result(data, chan, &res);
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if (ret < 0) {
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mutex_unlock(&data->lock);
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goto err;
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}
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buf[0] = res;
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mutex_unlock(&data->lock);
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iio_push_to_buffers_with_timestamp(indio_dev, buf, iio_get_time_ns());
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err:
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iio_trigger_notify_done(indio_dev->trig);
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return IRQ_HANDLED;
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}
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static int ads1015_set_scale(struct ads1015_data *data, int chan,
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int scale, int uscale)
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{
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int i, ret, rindex = -1;
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for (i = 0; i < ARRAY_SIZE(ads1015_scale); i++)
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if (ads1015_scale[i].scale == scale &&
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ads1015_scale[i].uscale == uscale) {
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rindex = i;
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break;
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}
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if (rindex < 0)
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return -EINVAL;
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ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
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ADS1015_CFG_PGA_MASK,
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rindex << ADS1015_CFG_PGA_SHIFT);
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if (ret < 0)
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return ret;
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data->channel_data[chan].pga = rindex;
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return 0;
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}
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static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
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{
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int i, ret, rindex = -1;
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for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++)
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if (ads1015_data_rate[i] == rate) {
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rindex = i;
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break;
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}
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if (rindex < 0)
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return -EINVAL;
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ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
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ADS1015_CFG_DR_MASK,
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rindex << ADS1015_CFG_DR_SHIFT);
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if (ret < 0)
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return ret;
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data->channel_data[chan].data_rate = rindex;
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return 0;
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}
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static int ads1015_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int *val,
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int *val2, long mask)
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{
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int ret, idx;
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struct ads1015_data *data = iio_priv(indio_dev);
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mutex_lock(&indio_dev->mlock);
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mutex_lock(&data->lock);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (iio_buffer_enabled(indio_dev)) {
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ret = -EBUSY;
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break;
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}
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ret = ads1015_set_power_state(data, true);
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if (ret < 0)
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break;
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ret = ads1015_get_adc_result(data, chan->address, val);
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if (ret < 0) {
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ads1015_set_power_state(data, false);
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break;
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}
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/* 12 bit res, D0 is bit 4 in conversion register */
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*val = sign_extend32(*val >> 4, 11);
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ret = ads1015_set_power_state(data, false);
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if (ret < 0)
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break;
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ret = IIO_VAL_INT;
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break;
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case IIO_CHAN_INFO_SCALE:
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idx = data->channel_data[chan->address].pga;
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*val = ads1015_scale[idx].scale;
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*val2 = ads1015_scale[idx].uscale;
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ret = IIO_VAL_INT_PLUS_MICRO;
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break;
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case IIO_CHAN_INFO_SAMP_FREQ:
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idx = data->channel_data[chan->address].data_rate;
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*val = ads1015_data_rate[idx];
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ret = IIO_VAL_INT;
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break;
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default:
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ret = -EINVAL;
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break;
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}
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mutex_unlock(&data->lock);
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mutex_unlock(&indio_dev->mlock);
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return ret;
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}
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static int ads1015_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan, int val,
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int val2, long mask)
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{
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struct ads1015_data *data = iio_priv(indio_dev);
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int ret;
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mutex_lock(&data->lock);
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switch (mask) {
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case IIO_CHAN_INFO_SCALE:
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ret = ads1015_set_scale(data, chan->address, val, val2);
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break;
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case IIO_CHAN_INFO_SAMP_FREQ:
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ret = ads1015_set_data_rate(data, chan->address, val);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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mutex_unlock(&data->lock);
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return ret;
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}
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static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
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{
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return ads1015_set_power_state(iio_priv(indio_dev), true);
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}
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static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
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{
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return ads1015_set_power_state(iio_priv(indio_dev), false);
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}
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static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
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.preenable = ads1015_buffer_preenable,
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.postenable = iio_triggered_buffer_postenable,
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.predisable = iio_triggered_buffer_predisable,
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.postdisable = ads1015_buffer_postdisable,
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.validate_scan_mask = &iio_validate_scan_mask_onehot,
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};
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static IIO_CONST_ATTR(scale_available, "3 2 1 0.5 0.25 0.125");
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static IIO_CONST_ATTR(sampling_frequency_available,
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"128 250 490 920 1600 2400 3300");
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static struct attribute *ads1015_attributes[] = {
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&iio_const_attr_scale_available.dev_attr.attr,
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&iio_const_attr_sampling_frequency_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group ads1015_attribute_group = {
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.attrs = ads1015_attributes,
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};
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static const struct iio_info ads1015_info = {
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.driver_module = THIS_MODULE,
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.read_raw = ads1015_read_raw,
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.write_raw = ads1015_write_raw,
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.attrs = &ads1015_attribute_group,
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};
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#ifdef CONFIG_OF
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static int ads1015_get_channels_config_of(struct i2c_client *client)
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{
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struct ads1015_data *data = i2c_get_clientdata(client);
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struct device_node *node;
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if (!client->dev.of_node ||
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!of_get_next_child(client->dev.of_node, NULL))
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return -EINVAL;
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for_each_child_of_node(client->dev.of_node, node) {
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u32 pval;
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unsigned int channel;
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unsigned int pga = ADS1015_DEFAULT_PGA;
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unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
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if (of_property_read_u32(node, "reg", &pval)) {
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dev_err(&client->dev, "invalid reg on %s\n",
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node->full_name);
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continue;
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}
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channel = pval;
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if (channel >= ADS1015_CHANNELS) {
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dev_err(&client->dev,
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"invalid channel index %d on %s\n",
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channel, node->full_name);
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continue;
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}
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if (!of_property_read_u32(node, "ti,gain", &pval)) {
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pga = pval;
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if (pga > 6) {
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dev_err(&client->dev, "invalid gain on %s\n",
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node->full_name);
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return -EINVAL;
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}
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}
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if (!of_property_read_u32(node, "ti,datarate", &pval)) {
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data_rate = pval;
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if (data_rate > 7) {
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dev_err(&client->dev,
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"invalid data_rate on %s\n",
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node->full_name);
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return -EINVAL;
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}
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}
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data->channel_data[channel].pga = pga;
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data->channel_data[channel].data_rate = data_rate;
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}
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return 0;
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}
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#endif
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static void ads1015_get_channels_config(struct i2c_client *client)
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{
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unsigned int k;
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struct iio_dev *indio_dev = i2c_get_clientdata(client);
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struct ads1015_data *data = iio_priv(indio_dev);
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struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
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/* prefer platform data */
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if (pdata) {
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memcpy(data->channel_data, pdata->channel_data,
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sizeof(data->channel_data));
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return;
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}
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#ifdef CONFIG_OF
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if (!ads1015_get_channels_config_of(client))
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return;
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#endif
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/* fallback on default configuration */
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for (k = 0; k < ADS1015_CHANNELS; ++k) {
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data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
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data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
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}
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}
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static int ads1015_probe(struct i2c_client *client,
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const struct i2c_device_id *id)
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{
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struct iio_dev *indio_dev;
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struct ads1015_data *data;
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int ret;
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indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
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if (!indio_dev)
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return -ENOMEM;
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data = iio_priv(indio_dev);
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i2c_set_clientdata(client, indio_dev);
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mutex_init(&data->lock);
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indio_dev->dev.parent = &client->dev;
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indio_dev->info = &ads1015_info;
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indio_dev->name = ADS1015_DRV_NAME;
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indio_dev->channels = ads1015_channels;
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indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
|
|
indio_dev->modes = INDIO_DIRECT_MODE;
|
|
|
|
/* we need to keep this ABI the same as used by hwmon ADS1015 driver */
|
|
ads1015_get_channels_config(client);
|
|
|
|
data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
|
|
if (IS_ERR(data->regmap)) {
|
|
dev_err(&client->dev, "Failed to allocate register map\n");
|
|
return PTR_ERR(data->regmap);
|
|
}
|
|
|
|
ret = iio_triggered_buffer_setup(indio_dev, NULL,
|
|
ads1015_trigger_handler,
|
|
&ads1015_buffer_setup_ops);
|
|
if (ret < 0) {
|
|
dev_err(&client->dev, "iio triggered buffer setup failed\n");
|
|
return ret;
|
|
}
|
|
ret = pm_runtime_set_active(&client->dev);
|
|
if (ret)
|
|
goto err_buffer_cleanup;
|
|
pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
|
|
pm_runtime_use_autosuspend(&client->dev);
|
|
pm_runtime_enable(&client->dev);
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
if (ret < 0) {
|
|
dev_err(&client->dev, "Failed to register IIO device\n");
|
|
goto err_buffer_cleanup;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_buffer_cleanup:
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int ads1015_remove(struct i2c_client *client)
|
|
{
|
|
struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
|
struct ads1015_data *data = iio_priv(indio_dev);
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
|
pm_runtime_disable(&client->dev);
|
|
pm_runtime_set_suspended(&client->dev);
|
|
pm_runtime_put_noidle(&client->dev);
|
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
|
|
/* power down single shot mode */
|
|
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
|
|
ADS1015_CFG_MOD_MASK,
|
|
ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int ads1015_runtime_suspend(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
|
|
struct ads1015_data *data = iio_priv(indio_dev);
|
|
|
|
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
|
|
ADS1015_CFG_MOD_MASK,
|
|
ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
|
|
}
|
|
|
|
static int ads1015_runtime_resume(struct device *dev)
|
|
{
|
|
struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
|
|
struct ads1015_data *data = iio_priv(indio_dev);
|
|
|
|
return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
|
|
ADS1015_CFG_MOD_MASK,
|
|
ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops ads1015_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
|
|
ads1015_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct i2c_device_id ads1015_id[] = {
|
|
{"ads1015", 0},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, ads1015_id);
|
|
|
|
static struct i2c_driver ads1015_driver = {
|
|
.driver = {
|
|
.name = ADS1015_DRV_NAME,
|
|
.pm = &ads1015_pm_ops,
|
|
},
|
|
.probe = ads1015_probe,
|
|
.remove = ads1015_remove,
|
|
.id_table = ads1015_id,
|
|
};
|
|
|
|
module_i2c_driver(ads1015_driver);
|
|
|
|
MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
|
|
MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
|
|
MODULE_LICENSE("GPL v2");
|