251 lines
7.1 KiB
C
251 lines
7.1 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui <ray.huang@amd.com>
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*
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/gfp.h>
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#include "smumgr.h"
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#include "iceland_smumgr.h"
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#include "pp_debug.h"
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#include "smu_ucode_xfer_vi.h"
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#include "ppsmc.h"
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#include "smu/smu_7_1_1_d.h"
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#include "smu/smu_7_1_1_sh_mask.h"
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#include "cgs_common.h"
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#include "iceland_smc.h"
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#define ICELAND_SMC_SIZE 0x20000
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static int iceland_start_smc(struct pp_smumgr *smumgr)
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{
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SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL, rst_reg, 0);
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return 0;
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}
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static void iceland_reset_smc(struct pp_smumgr *smumgr)
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{
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SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_RESET_CNTL,
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rst_reg, 1);
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}
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static void iceland_stop_smc_clock(struct pp_smumgr *smumgr)
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{
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SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_CLOCK_CNTL_0,
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ck_disable, 1);
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}
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static void iceland_start_smc_clock(struct pp_smumgr *smumgr)
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{
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SMUM_WRITE_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC,
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SMC_SYSCON_CLOCK_CNTL_0,
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ck_disable, 0);
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}
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static int iceland_smu_start_smc(struct pp_smumgr *smumgr)
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{
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/* set smc instruct start point at 0x0 */
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smu7_program_jump_on_start(smumgr);
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/* enable smc clock */
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iceland_start_smc_clock(smumgr);
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/* de-assert reset */
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iceland_start_smc(smumgr);
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SMUM_WAIT_INDIRECT_FIELD(smumgr, SMC_IND, FIRMWARE_FLAGS,
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INTERRUPTS_ENABLED, 1);
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return 0;
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}
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static int iceland_upload_smc_firmware_data(struct pp_smumgr *smumgr,
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uint32_t length, const uint8_t *src,
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uint32_t limit, uint32_t start_addr)
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{
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uint32_t byte_count = length;
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uint32_t data;
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PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
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cgs_write_register(smumgr->device, mmSMC_IND_INDEX_0, start_addr);
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SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
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while (byte_count >= 4) {
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data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3];
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cgs_write_register(smumgr->device, mmSMC_IND_DATA_0, data);
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src += 4;
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byte_count -= 4;
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}
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SMUM_WRITE_FIELD(smumgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
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PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be dividable by 4.", return -EINVAL);
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return 0;
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}
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static int iceland_smu_upload_firmware_image(struct pp_smumgr *smumgr)
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{
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uint32_t val;
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struct cgs_firmware_info info = {0};
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if (smumgr == NULL || smumgr->device == NULL)
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return -EINVAL;
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/* load SMC firmware */
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cgs_get_firmware_info(smumgr->device,
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smu7_convert_fw_type_to_cgs(UCODE_ID_SMU), &info);
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if (info.image_size & 3) {
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pr_err("[ powerplay ] SMC ucode is not 4 bytes aligned\n");
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return -EINVAL;
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}
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if (info.image_size > ICELAND_SMC_SIZE) {
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pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
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return -EINVAL;
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}
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/* wait for smc boot up */
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SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND,
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RCU_UC_EVENTS, boot_seq_done, 0);
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/* clear firmware interrupt enable flag */
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val = cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC,
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ixSMC_SYSCON_MISC_CNTL);
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cgs_write_ind_register(smumgr->device, CGS_IND_REG__SMC,
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ixSMC_SYSCON_MISC_CNTL, val | 1);
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/* stop smc clock */
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iceland_stop_smc_clock(smumgr);
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/* reset smc */
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iceland_reset_smc(smumgr);
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iceland_upload_smc_firmware_data(smumgr, info.image_size,
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(uint8_t *)info.kptr, ICELAND_SMC_SIZE,
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info.ucode_start_address);
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return 0;
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}
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static int iceland_request_smu_load_specific_fw(struct pp_smumgr *smumgr,
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uint32_t firmwareType)
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{
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return 0;
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}
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static int iceland_start_smu(struct pp_smumgr *smumgr)
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{
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int result;
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result = iceland_smu_upload_firmware_image(smumgr);
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if (result)
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return result;
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result = iceland_smu_start_smc(smumgr);
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if (result)
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return result;
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if (!smu7_is_smc_ram_running(smumgr)) {
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printk("smu not running, upload firmware again \n");
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result = iceland_smu_upload_firmware_image(smumgr);
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if (result)
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return result;
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result = iceland_smu_start_smc(smumgr);
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if (result)
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return result;
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}
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result = smu7_request_smu_load_fw(smumgr);
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return result;
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}
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/**
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* Write a 32bit value to the SMC SRAM space.
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* ALL PARAMETERS ARE IN HOST BYTE ORDER.
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* @param smumgr the address of the powerplay hardware manager.
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* @param smcAddress the address in the SMC RAM to access.
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* @param value to write to the SMC SRAM.
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*/
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static int iceland_smu_init(struct pp_smumgr *smumgr)
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{
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int i;
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struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(smumgr->backend);
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if (smu7_init(smumgr))
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return -EINVAL;
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for (i = 0; i < SMU71_MAX_LEVELS_GRAPHICS; i++)
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smu_data->activity_target[i] = 30;
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return 0;
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}
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static const struct pp_smumgr_func iceland_smu_funcs = {
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.smu_init = &iceland_smu_init,
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.smu_fini = &smu7_smu_fini,
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.start_smu = &iceland_start_smu,
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.check_fw_load_finish = &smu7_check_fw_load_finish,
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.request_smu_load_fw = &smu7_reload_firmware,
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.request_smu_load_specific_fw = &iceland_request_smu_load_specific_fw,
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.send_msg_to_smc = &smu7_send_msg_to_smc,
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.send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
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.download_pptable_settings = NULL,
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.upload_pptable_settings = NULL,
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.get_offsetof = iceland_get_offsetof,
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.process_firmware_header = iceland_process_firmware_header,
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.init_smc_table = iceland_init_smc_table,
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.update_sclk_threshold = iceland_update_sclk_threshold,
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.thermal_setup_fan_table = iceland_thermal_setup_fan_table,
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.populate_all_graphic_levels = iceland_populate_all_graphic_levels,
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.populate_all_memory_levels = iceland_populate_all_memory_levels,
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.get_mac_definition = iceland_get_mac_definition,
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.initialize_mc_reg_table = iceland_initialize_mc_reg_table,
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.is_dpm_running = iceland_is_dpm_running,
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};
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int iceland_smum_init(struct pp_smumgr *smumgr)
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{
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struct iceland_smumgr *iceland_smu = NULL;
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iceland_smu = kzalloc(sizeof(struct iceland_smumgr), GFP_KERNEL);
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if (iceland_smu == NULL)
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return -ENOMEM;
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smumgr->backend = iceland_smu;
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smumgr->smumgr_funcs = &iceland_smu_funcs;
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return 0;
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}
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