164 lines
4.5 KiB
C
164 lines
4.5 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NLM_HAL_HALDEFS_H__
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#define __NLM_HAL_HALDEFS_H__
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/*
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* This file contains platform specific memory mapped IO implementation
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* and will provide a way to read 32/64 bit memory mapped registers in
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* all ABIs
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*/
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#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
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#error "o32 compile not supported on XLP yet"
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#endif
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/*
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* For o32 compilation, we have to disable interrupts and enable KX bit to
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* access 64 bit addresses or data.
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*
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* We need to disable interrupts because we save just the lower 32 bits of
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* registers in interrupt handling. So if we get hit by an interrupt while
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* using the upper 32 bits of a register, we lose.
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*/
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static inline uint32_t nlm_save_flags_kx(void)
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{
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return change_c0_status(ST0_KX | ST0_IE, ST0_KX);
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}
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static inline uint32_t nlm_save_flags_cop2(void)
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{
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return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2);
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}
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static inline void nlm_restore_flags(uint32_t sr)
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{
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write_c0_status(sr);
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}
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/*
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* The n64 implementations are simple, the o32 implementations when they
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* are added, will have to disable interrupts and enable KX before doing
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* 64 bit ops.
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*/
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static inline uint32_t
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nlm_read_reg(uint64_t base, uint32_t reg)
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{
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
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return *addr;
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}
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static inline void
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nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
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{
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
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*addr = val;
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}
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static inline uint64_t
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nlm_read_reg64(uint64_t base, uint32_t reg)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
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return *ptr;
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}
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static inline void
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nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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volatile uint64_t *ptr = (volatile uint64_t *)(long)addr;
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*ptr = val;
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}
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/*
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* Routines to store 32/64 bit values to 64 bit addresses,
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* used when going thru XKPHYS to access registers
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*/
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static inline uint32_t
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nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
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{
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return nlm_read_reg(base, reg);
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}
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static inline void
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nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
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{
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nlm_write_reg(base, reg, val);
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}
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static inline uint64_t
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nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
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{
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return nlm_read_reg64(base, reg);
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}
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static inline void
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nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
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{
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nlm_write_reg64(base, reg, val);
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}
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/* Location where IO base is mapped */
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extern uint64_t nlm_io_base;
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#if defined(CONFIG_CPU_XLP)
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static inline uint64_t
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nlm_pcicfg_base(uint32_t devoffset)
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{
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return nlm_io_base + devoffset;
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}
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static inline uint64_t
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nlm_xkphys_map_pcibar0(uint64_t pcibase)
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{
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uint64_t paddr;
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paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
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return (uint64_t)0x9000000000000000 | paddr;
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}
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#elif defined(CONFIG_CPU_XLR)
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static inline uint64_t
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nlm_mmio_base(uint32_t devoffset)
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{
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return nlm_io_base + devoffset;
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}
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#endif
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#endif
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