298 lines
6.1 KiB
ArmAsm
298 lines
6.1 KiB
ArmAsm
/*
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* This file contains assembly-language implementations
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* of IP-style 1's complement checksum routines.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au).
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*/
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#include <linux/sys.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/errno.h>
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#include <asm/ppc_asm.h>
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.text
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/*
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* computes the checksum of a memory block at buff, length len,
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* and adds in "sum" (32-bit)
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*
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* __csum_partial(buff, len, sum)
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*/
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_GLOBAL(__csum_partial)
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subi r3,r3,4
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srawi. r6,r4,2 /* Divide len by 4 and also clear carry */
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beq 3f /* if we're doing < 4 bytes */
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andi. r0,r3,2 /* Align buffer to longword boundary */
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beq+ 1f
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lhz r0,4(r3) /* do 2 bytes to get aligned */
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subi r4,r4,2
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addi r3,r3,2
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srwi. r6,r4,2 /* # words to do */
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adde r5,r5,r0
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beq 3f
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1: andi. r6,r6,3 /* Prepare to handle words 4 by 4 */
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beq 21f
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mtctr r6
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2: lwzu r0,4(r3)
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adde r5,r5,r0
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bdnz 2b
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21: srwi. r6,r4,4 /* # blocks of 4 words to do */
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beq 3f
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mtctr r6
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22: lwz r0,4(r3)
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lwz r6,8(r3)
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lwz r7,12(r3)
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lwzu r8,16(r3)
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adde r5,r5,r0
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adde r5,r5,r6
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adde r5,r5,r7
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adde r5,r5,r8
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bdnz 22b
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3: andi. r0,r4,2
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beq+ 4f
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lhz r0,4(r3)
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addi r3,r3,2
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adde r5,r5,r0
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4: andi. r0,r4,1
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beq+ 5f
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lbz r0,4(r3)
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slwi r0,r0,8 /* Upper byte of word */
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adde r5,r5,r0
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5: addze r3,r5 /* add in final carry */
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blr
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/*
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* Computes the checksum of a memory block at src, length len,
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* and adds in "sum" (32-bit), while copying the block to dst.
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* If an access exception occurs on src or dst, it stores -EFAULT
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* to *src_err or *dst_err respectively, and (for an error on
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* src) zeroes the rest of dst.
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*
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* csum_partial_copy_generic(src, dst, len, sum, src_err, dst_err)
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*/
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#define CSUM_COPY_16_BYTES_WITHEX(n) \
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8 ## n ## 0: \
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lwz r7,4(r4); \
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8 ## n ## 1: \
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lwz r8,8(r4); \
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8 ## n ## 2: \
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lwz r9,12(r4); \
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8 ## n ## 3: \
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lwzu r10,16(r4); \
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8 ## n ## 4: \
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stw r7,4(r6); \
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adde r12,r12,r7; \
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8 ## n ## 5: \
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stw r8,8(r6); \
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adde r12,r12,r8; \
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8 ## n ## 6: \
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stw r9,12(r6); \
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adde r12,r12,r9; \
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8 ## n ## 7: \
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stwu r10,16(r6); \
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adde r12,r12,r10
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#define CSUM_COPY_16_BYTES_EXCODE(n) \
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.section __ex_table,"a"; \
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.align 2; \
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.long 8 ## n ## 0b,src_error; \
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.long 8 ## n ## 1b,src_error; \
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.long 8 ## n ## 2b,src_error; \
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.long 8 ## n ## 3b,src_error; \
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.long 8 ## n ## 4b,dst_error; \
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.long 8 ## n ## 5b,dst_error; \
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.long 8 ## n ## 6b,dst_error; \
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.long 8 ## n ## 7b,dst_error; \
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.text
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.text
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.stabs "arch/powerpc/lib/",N_SO,0,0,0f
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.stabs "checksum_32.S",N_SO,0,0,0f
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0:
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CACHELINE_BYTES = L1_CACHE_BYTES
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LG_CACHELINE_BYTES = L1_CACHE_SHIFT
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CACHELINE_MASK = (L1_CACHE_BYTES-1)
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_GLOBAL(csum_partial_copy_generic)
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stwu r1,-16(r1)
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stw r7,12(r1)
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stw r8,8(r1)
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andi. r0,r4,1 /* is destination address even ? */
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cmplwi cr7,r0,0
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addic r12,r6,0
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addi r6,r4,-4
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neg r0,r4
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addi r4,r3,-4
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andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */
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beq 58f
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cmplw 0,r5,r0 /* is this more than total to do? */
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blt 63f /* if not much to do */
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andi. r8,r0,3 /* get it word-aligned first */
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mtctr r8
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beq+ 61f
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li r3,0
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70: lbz r9,4(r4) /* do some bytes */
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addi r4,r4,1
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slwi r3,r3,8
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rlwimi r3,r9,0,24,31
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71: stb r9,4(r6)
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addi r6,r6,1
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bdnz 70b
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adde r12,r12,r3
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61: subf r5,r0,r5
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srwi. r0,r0,2
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mtctr r0
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beq 58f
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72: lwzu r9,4(r4) /* do some words */
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adde r12,r12,r9
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73: stwu r9,4(r6)
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bdnz 72b
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58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */
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clrlwi r5,r5,32-LG_CACHELINE_BYTES
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li r11,4
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beq 63f
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/* Here we decide how far ahead to prefetch the source */
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li r3,4
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cmpwi r0,1
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li r7,0
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ble 114f
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li r7,1
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#if MAX_COPY_PREFETCH > 1
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/* Heuristically, for large transfers we prefetch
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MAX_COPY_PREFETCH cachelines ahead. For small transfers
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we prefetch 1 cacheline ahead. */
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cmpwi r0,MAX_COPY_PREFETCH
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ble 112f
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li r7,MAX_COPY_PREFETCH
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112: mtctr r7
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111: dcbt r3,r4
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addi r3,r3,CACHELINE_BYTES
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bdnz 111b
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#else
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dcbt r3,r4
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addi r3,r3,CACHELINE_BYTES
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#endif /* MAX_COPY_PREFETCH > 1 */
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114: subf r8,r7,r0
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mr r0,r7
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mtctr r8
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53: dcbt r3,r4
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54: dcbz r11,r6
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/* the main body of the cacheline loop */
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CSUM_COPY_16_BYTES_WITHEX(0)
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#if L1_CACHE_BYTES >= 32
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CSUM_COPY_16_BYTES_WITHEX(1)
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#if L1_CACHE_BYTES >= 64
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CSUM_COPY_16_BYTES_WITHEX(2)
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CSUM_COPY_16_BYTES_WITHEX(3)
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#if L1_CACHE_BYTES >= 128
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CSUM_COPY_16_BYTES_WITHEX(4)
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CSUM_COPY_16_BYTES_WITHEX(5)
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CSUM_COPY_16_BYTES_WITHEX(6)
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CSUM_COPY_16_BYTES_WITHEX(7)
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#endif
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#endif
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#endif
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bdnz 53b
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cmpwi r0,0
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li r3,4
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li r7,0
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bne 114b
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63: srwi. r0,r5,2
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mtctr r0
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beq 64f
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30: lwzu r0,4(r4)
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adde r12,r12,r0
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31: stwu r0,4(r6)
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bdnz 30b
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64: andi. r0,r5,2
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beq+ 65f
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40: lhz r0,4(r4)
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addi r4,r4,2
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41: sth r0,4(r6)
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adde r12,r12,r0
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addi r6,r6,2
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65: andi. r0,r5,1
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beq+ 66f
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50: lbz r0,4(r4)
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51: stb r0,4(r6)
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slwi r0,r0,8
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adde r12,r12,r0
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66: addze r3,r12
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addi r1,r1,16
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beqlr+ cr7
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rlwinm r3,r3,8,0,31 /* swap bytes for odd destination */
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blr
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/* read fault */
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src_error:
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lwz r7,12(r1)
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addi r1,r1,16
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cmpwi cr0,r7,0
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beqlr
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li r0,-EFAULT
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stw r0,0(r7)
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blr
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/* write fault */
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dst_error:
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lwz r8,8(r1)
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addi r1,r1,16
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cmpwi cr0,r8,0
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beqlr
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li r0,-EFAULT
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stw r0,0(r8)
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blr
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.section __ex_table,"a"
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.align 2
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.long 70b,src_error
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.long 71b,dst_error
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.long 72b,src_error
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.long 73b,dst_error
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.long 54b,dst_error
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.text
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/*
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* this stuff handles faults in the cacheline loop and branches to either
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* src_error (if in read part) or dst_error (if in write part)
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*/
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CSUM_COPY_16_BYTES_EXCODE(0)
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#if L1_CACHE_BYTES >= 32
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CSUM_COPY_16_BYTES_EXCODE(1)
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#if L1_CACHE_BYTES >= 64
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CSUM_COPY_16_BYTES_EXCODE(2)
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CSUM_COPY_16_BYTES_EXCODE(3)
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#if L1_CACHE_BYTES >= 128
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CSUM_COPY_16_BYTES_EXCODE(4)
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CSUM_COPY_16_BYTES_EXCODE(5)
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CSUM_COPY_16_BYTES_EXCODE(6)
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CSUM_COPY_16_BYTES_EXCODE(7)
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#endif
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#endif
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#endif
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.section __ex_table,"a"
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.align 2
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.long 30b,src_error
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.long 31b,dst_error
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.long 40b,src_error
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.long 41b,dst_error
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.long 50b,src_error
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.long 51b,dst_error
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