261 lines
8.0 KiB
C
261 lines
8.0 KiB
C
/*
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* Internal header file for Samsung S3C2410 serial ports (UART0-2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
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*
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* Adapted from:
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*
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* Internal header file for MX1ADS serial ports (UART1 & 2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_REGS_SERIAL_H
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#define __ASM_ARM_REGS_SERIAL_H
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#define S3C2410_URXH (0x24)
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#define S3C2410_UTXH (0x20)
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#define S3C2410_ULCON (0x00)
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#define S3C2410_UCON (0x04)
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#define S3C2410_UFCON (0x08)
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#define S3C2410_UMCON (0x0C)
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#define S3C2410_UBRDIV (0x28)
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#define S3C2410_UTRSTAT (0x10)
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#define S3C2410_UERSTAT (0x14)
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#define S3C2410_UFSTAT (0x18)
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#define S3C2410_UMSTAT (0x1C)
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#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
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#define S3C2410_LCON_CS5 (0x0)
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#define S3C2410_LCON_CS6 (0x1)
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#define S3C2410_LCON_CS7 (0x2)
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#define S3C2410_LCON_CS8 (0x3)
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#define S3C2410_LCON_CSMASK (0x3)
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#define S3C2410_LCON_PNONE (0x0)
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#define S3C2410_LCON_PEVEN (0x5 << 3)
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#define S3C2410_LCON_PODD (0x4 << 3)
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#define S3C2410_LCON_PMASK (0x7 << 3)
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#define S3C2410_LCON_STOPB (1<<2)
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#define S3C2410_LCON_IRM (1<<6)
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#define S3C2440_UCON_CLKMASK (3<<10)
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#define S3C2440_UCON_CLKSHIFT (10)
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#define S3C2440_UCON_PCLK (0<<10)
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#define S3C2440_UCON_UCLK (1<<10)
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#define S3C2440_UCON_PCLK2 (2<<10)
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#define S3C2440_UCON_FCLK (3<<10)
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#define S3C2443_UCON_EPLL (3<<10)
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#define S3C6400_UCON_CLKMASK (3<<10)
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#define S3C6400_UCON_CLKSHIFT (10)
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#define S3C6400_UCON_PCLK (0<<10)
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#define S3C6400_UCON_PCLK2 (2<<10)
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#define S3C6400_UCON_UCLK0 (1<<10)
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#define S3C6400_UCON_UCLK1 (3<<10)
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#define S3C2440_UCON2_FCLK_EN (1<<15)
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#define S3C2440_UCON0_DIVMASK (15 << 12)
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#define S3C2440_UCON1_DIVMASK (15 << 12)
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#define S3C2440_UCON2_DIVMASK (7 << 12)
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#define S3C2440_UCON_DIVSHIFT (12)
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#define S3C2412_UCON_CLKMASK (3<<10)
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#define S3C2412_UCON_CLKSHIFT (10)
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#define S3C2412_UCON_UCLK (1<<10)
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#define S3C2412_UCON_USYSCLK (3<<10)
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#define S3C2412_UCON_PCLK (0<<10)
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#define S3C2412_UCON_PCLK2 (2<<10)
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#define S3C2410_UCON_CLKMASK (1 << 10)
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#define S3C2410_UCON_CLKSHIFT (10)
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#define S3C2410_UCON_UCLK (1<<10)
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#define S3C2410_UCON_SBREAK (1<<4)
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#define S3C2410_UCON_TXILEVEL (1<<9)
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#define S3C2410_UCON_RXILEVEL (1<<8)
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#define S3C2410_UCON_TXIRQMODE (1<<2)
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#define S3C2410_UCON_RXIRQMODE (1<<0)
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#define S3C2410_UCON_RXFIFO_TOI (1<<7)
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#define S3C2443_UCON_RXERR_IRQEN (1<<6)
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#define S3C2443_UCON_LOOPBACK (1<<5)
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#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI)
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#define S3C2410_UFCON_FIFOMODE (1<<0)
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#define S3C2410_UFCON_TXTRIG0 (0<<6)
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#define S3C2410_UFCON_RXTRIG8 (1<<4)
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#define S3C2410_UFCON_RXTRIG12 (2<<4)
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/* S3C2440 FIFO trigger levels */
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#define S3C2440_UFCON_RXTRIG1 (0<<4)
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#define S3C2440_UFCON_RXTRIG8 (1<<4)
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#define S3C2440_UFCON_RXTRIG16 (2<<4)
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#define S3C2440_UFCON_RXTRIG32 (3<<4)
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#define S3C2440_UFCON_TXTRIG0 (0<<6)
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#define S3C2440_UFCON_TXTRIG16 (1<<6)
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#define S3C2440_UFCON_TXTRIG32 (2<<6)
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#define S3C2440_UFCON_TXTRIG48 (3<<6)
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#define S3C2410_UFCON_RESETBOTH (3<<1)
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#define S3C2410_UFCON_RESETTX (1<<2)
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#define S3C2410_UFCON_RESETRX (1<<1)
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#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S3C2410_UFCON_TXTRIG0 | \
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S3C2410_UFCON_RXTRIG8 )
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#define S3C2410_UMCOM_AFC (1<<4)
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#define S3C2410_UMCOM_RTS_LOW (1<<0)
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#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
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#define S3C2412_UMCON_AFC_56 (1<<5)
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#define S3C2412_UMCON_AFC_48 (2<<5)
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#define S3C2412_UMCON_AFC_40 (3<<5)
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#define S3C2412_UMCON_AFC_32 (4<<5)
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#define S3C2412_UMCON_AFC_24 (5<<5)
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#define S3C2412_UMCON_AFC_16 (6<<5)
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#define S3C2412_UMCON_AFC_8 (7<<5)
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#define S3C2410_UFSTAT_TXFULL (1<<9)
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#define S3C2410_UFSTAT_RXFULL (1<<8)
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#define S3C2410_UFSTAT_TXMASK (15<<4)
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#define S3C2410_UFSTAT_TXSHIFT (4)
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#define S3C2410_UFSTAT_RXMASK (15<<0)
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#define S3C2410_UFSTAT_RXSHIFT (0)
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/* UFSTAT S3C2443 same as S3C2440 */
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#define S3C2440_UFSTAT_TXFULL (1<<14)
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#define S3C2440_UFSTAT_RXFULL (1<<6)
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#define S3C2440_UFSTAT_TXSHIFT (8)
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#define S3C2440_UFSTAT_RXSHIFT (0)
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#define S3C2440_UFSTAT_TXMASK (63<<8)
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#define S3C2440_UFSTAT_RXMASK (63)
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#define S3C2410_UTRSTAT_TXE (1<<2)
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#define S3C2410_UTRSTAT_TXFE (1<<1)
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#define S3C2410_UTRSTAT_RXDR (1<<0)
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#define S3C2410_UERSTAT_OVERRUN (1<<0)
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#define S3C2410_UERSTAT_FRAME (1<<2)
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#define S3C2410_UERSTAT_BREAK (1<<3)
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#define S3C2443_UERSTAT_PARITY (1<<1)
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#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
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S3C2410_UERSTAT_FRAME | \
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S3C2410_UERSTAT_BREAK)
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#define S3C2410_UMSTAT_CTS (1<<0)
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#define S3C2410_UMSTAT_DeltaCTS (1<<2)
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#define S3C2443_DIVSLOT (0x2C)
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/* S3C64XX interrupt registers. */
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#define S3C64XX_UINTP 0x30
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#define S3C64XX_UINTSP 0x34
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#define S3C64XX_UINTM 0x38
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#define S3C64XX_UINTM_RXD (0)
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#define S3C64XX_UINTM_TXD (2)
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#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
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#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
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/* Following are specific to S5PV210 */
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#define S5PV210_UCON_CLKMASK (1<<10)
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#define S5PV210_UCON_CLKSHIFT (10)
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#define S5PV210_UCON_PCLK (0<<10)
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#define S5PV210_UCON_UCLK (1<<10)
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#define S5PV210_UFCON_TXTRIG0 (0<<8)
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#define S5PV210_UFCON_TXTRIG4 (1<<8)
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#define S5PV210_UFCON_TXTRIG8 (2<<8)
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#define S5PV210_UFCON_TXTRIG16 (3<<8)
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#define S5PV210_UFCON_TXTRIG32 (4<<8)
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#define S5PV210_UFCON_TXTRIG64 (5<<8)
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#define S5PV210_UFCON_TXTRIG128 (6<<8)
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#define S5PV210_UFCON_TXTRIG256 (7<<8)
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#define S5PV210_UFCON_RXTRIG1 (0<<4)
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#define S5PV210_UFCON_RXTRIG4 (1<<4)
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#define S5PV210_UFCON_RXTRIG8 (2<<4)
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#define S5PV210_UFCON_RXTRIG16 (3<<4)
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#define S5PV210_UFCON_RXTRIG32 (4<<4)
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#define S5PV210_UFCON_RXTRIG64 (5<<4)
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#define S5PV210_UFCON_RXTRIG128 (6<<4)
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#define S5PV210_UFCON_RXTRIG256 (7<<4)
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#define S5PV210_UFSTAT_TXFULL (1<<24)
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#define S5PV210_UFSTAT_RXFULL (1<<8)
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#define S5PV210_UFSTAT_TXMASK (255<<16)
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#define S5PV210_UFSTAT_TXSHIFT (16)
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#define S5PV210_UFSTAT_RXMASK (255<<0)
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#define S5PV210_UFSTAT_RXSHIFT (0)
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#define S3C2410_UCON_CLKSEL0 (1 << 0)
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#define S3C2410_UCON_CLKSEL1 (1 << 1)
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#define S3C2410_UCON_CLKSEL2 (1 << 2)
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#define S3C2410_UCON_CLKSEL3 (1 << 3)
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/* Default values for s5pv210 UCON and UFCON uart registers */
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#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI | \
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S3C2443_UCON_RXERR_IRQEN)
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#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S5PV210_UFCON_TXTRIG4 | \
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S5PV210_UFCON_RXTRIG4)
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#ifndef __ASSEMBLY__
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/* configuration structure for per-machine configurations for the
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* serial port
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*
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* the pointer is setup by the machine specific initialisation from the
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* arch/arm/mach-s3c2410/ directory.
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*/
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struct s3c2410_uartcfg {
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unsigned char hwport; /* hardware port number */
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unsigned char unused;
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unsigned short flags;
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upf_t uart_flags; /* default uart flags */
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unsigned int clk_sel;
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unsigned int has_fracval;
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unsigned long ucon; /* value of ucon for port */
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unsigned long ulcon; /* value of ulcon for port */
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unsigned long ufcon; /* value of ufcon for port */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_REGS_SERIAL_H */
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