375 lines
9.0 KiB
Plaintext
375 lines
9.0 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Contains definitions specific to the Armada XP SoC that are not
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* common to all Armada SoCs.
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*/
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#include "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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aliases {
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serial2 = &uart2;
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serial3 = &uart3;
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};
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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internal-regs {
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sdramc@1400 {
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compatible = "marvell,armada-xp-sdram-controller";
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reg = <0x1400 0x500>;
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};
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L2: l2-cache {
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compatible = "marvell,aurora-system-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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cache-level = <2>;
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cache-unified;
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wt-override;
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};
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spi0: spi@10600 {
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compatible = "marvell,armada-xp-spi",
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"marvell,orion-spi";
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-xp-spi",
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"marvell,orion-spi";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x100>;
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x100>;
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};
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uart2: serial@12200 {
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compatible = "snps,dw-apb-uart";
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "snps,dw-apb-uart";
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pinctrl-0 = <&uart3_pins>;
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pinctrl-names = "default";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x500>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,armada-xp-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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thermal@182b0 {
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compatible = "marvell,armadaxp-thermal";
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reg = <0x182b0 0x4
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0x184d0 0x4>;
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status = "okay";
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};
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cpuclk: clock-complex@18700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0x18700 0x24>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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};
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interrupt-controller@20a00 {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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timer@20300 {
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compatible = "marvell,armada-xp-timer";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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watchdog@20300 {
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compatible = "marvell,armada-xp-wdt";
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x20>;
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};
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cpu-config@21000 {
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compatible = "marvell,armada-xp-cpu-config";
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reg = <0x21000 0x8>;
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};
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eth2: ethernet@30000 {
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compatible = "marvell,armada-xp-neta";
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reg = <0x30000 0x4000>;
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interrupts = <12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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};
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usb@50000 {
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clocks = <&gateclk 18>;
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};
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usb@51000 {
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clocks = <&gateclk 19>;
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};
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usb@52000 {
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compatible = "marvell,orion-ehci";
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reg = <0x52000 0x500>;
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interrupts = <47>;
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clocks = <&gateclk 20>;
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status = "disabled";
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor10 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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ethernet@70000 {
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compatible = "marvell,armada-xp-neta";
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};
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ethernet@74000 {
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compatible = "marvell,armada-xp-neta";
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};
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crypto@90000 {
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compatible = "marvell,armada-xp-crypto";
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reg = <0x90000 0x10000>;
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reg-names = "regs";
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interrupts = <48>, <49>;
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clocks = <&gateclk 23>, <&gateclk 23>;
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clock-names = "cesa0", "cesa1";
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marvell,crypto-srams = <&crypto_sram0>,
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<&crypto_sram1>;
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marvell,crypto-sram-size = <0x800>;
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};
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bm: bm@c0000 {
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compatible = "marvell,armada-380-neta-bm";
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reg = <0xc0000 0xac>;
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clocks = <&gateclk 13>;
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internal-mem = <&bm_bppi>;
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status = "disabled";
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};
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xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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0xF0B00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor00 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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};
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crypto_sram0: sa-sram0 {
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compatible = "mmio-sram";
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reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
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clocks = <&gateclk 23>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
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};
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crypto_sram1: sa-sram1 {
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compatible = "mmio-sram";
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reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
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clocks = <&gateclk 23>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
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};
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bm_bppi: bm-bppi {
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compatible = "mmio-sram";
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reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
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ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&gateclk 13>;
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no-memory-wc;
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status = "disabled";
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};
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};
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clocks {
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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};
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&pinctrl {
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ge0_gmii_pins: ge0-gmii-pins {
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marvell,pins =
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"mpp0", "mpp1", "mpp2", "mpp3",
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"mpp4", "mpp5", "mpp6", "mpp7",
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"mpp8", "mpp9", "mpp10", "mpp11",
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"mpp12", "mpp13", "mpp14", "mpp15",
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"mpp16", "mpp17", "mpp18", "mpp19",
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"mpp20", "mpp21", "mpp22", "mpp23";
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marvell,function = "ge0";
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};
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ge0_rgmii_pins: ge0-rgmii-pins {
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marvell,pins =
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"mpp0", "mpp1", "mpp2", "mpp3",
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"mpp4", "mpp5", "mpp6", "mpp7",
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"mpp8", "mpp9", "mpp10", "mpp11";
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marvell,function = "ge0";
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};
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ge1_rgmii_pins: ge1-rgmii-pins {
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marvell,pins =
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"mpp12", "mpp13", "mpp14", "mpp15",
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"mpp16", "mpp17", "mpp18", "mpp19",
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"mpp20", "mpp21", "mpp22", "mpp23";
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marvell,function = "ge1";
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};
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sdio_pins: sdio-pins {
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marvell,pins = "mpp30", "mpp31", "mpp32",
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"mpp33", "mpp34", "mpp35";
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marvell,function = "sd0";
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};
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spi0_pins: spi0-pins {
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marvell,pins = "mpp36", "mpp37",
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"mpp38", "mpp39";
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marvell,function = "spi0";
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};
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uart2_pins: uart2-pins {
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marvell,pins = "mpp42", "mpp43";
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marvell,function = "uart2";
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};
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uart3_pins: uart3-pins {
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marvell,pins = "mpp44", "mpp45";
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marvell,function = "uart3";
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};
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};
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