387 lines
9.4 KiB
ArmAsm
387 lines
9.4 KiB
ArmAsm
/* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 by Helge Deller
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* Copyright 1999 SuSE GmbH (Philipp Rumpf)
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* Copyright 1999 Philipp Rumpf (prumpf@tux.org)
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* Copyright 2000 Hewlett Packard (Paul Bame, bame@puffin.external.hp.com)
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* Copyright (C) 2001 Grant Grundler (Hewlett Packard)
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* Copyright (C) 2004 Kyle McMartin <kyle@debian.org>
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*
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* Initial Version 04-23-1999 by Helge Deller <deller@gmx.de>
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*/
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#include <linux/autoconf.h> /* for CONFIG_SMP */
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#include <asm/offsets.h>
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#include <asm/psw.h>
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#include <asm/pdc.h>
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#include <asm/assembly.h>
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#include <asm/pgtable.h>
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.level LEVEL
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.data
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.export boot_args
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boot_args:
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.word 0 /* arg0 */
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.word 0 /* arg1 */
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.word 0 /* arg2 */
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.word 0 /* arg3 */
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.text
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.align 4
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.import init_thread_union,data
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.import fault_vector_20,code /* IVA parisc 2.0 32 bit */
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#ifndef __LP64__
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.import fault_vector_11,code /* IVA parisc 1.1 32 bit */
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.import $global$ /* forward declaration */
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#endif /*!LP64*/
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.export stext
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.export _stext,data /* Kernel want it this way! */
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_stext:
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stext:
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.proc
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.callinfo
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/* Make sure sr4-sr7 are set to zero for the kernel address space */
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mtsp %r0,%sr4
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mtsp %r0,%sr5
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mtsp %r0,%sr6
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mtsp %r0,%sr7
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/* Clear BSS (shouldn't the boot loader do this?) */
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.import __bss_start,data
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.import __bss_stop,data
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load32 PA(__bss_start),%r3
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load32 PA(__bss_stop),%r4
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$bss_loop:
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cmpb,<<,n %r3,%r4,$bss_loop
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stw,ma %r0,4(%r3)
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/* Save away the arguments the boot loader passed in (32 bit args) */
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load32 PA(boot_args),%r1
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stw,ma %arg0,4(%r1)
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stw,ma %arg1,4(%r1)
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stw,ma %arg2,4(%r1)
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stw,ma %arg3,4(%r1)
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/* Initialize startup VM. Just map first 8/16 MB of memory */
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load32 PA(swapper_pg_dir),%r4
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mtctl %r4,%cr24 /* Initialize kernel root pointer */
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mtctl %r4,%cr25 /* Initialize user root pointer */
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#ifdef __LP64__
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/* Set pmd in pgd */
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load32 PA(pmd0),%r5
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shrd %r5,PxD_VALUE_SHIFT,%r3
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ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
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stw %r3,ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4)
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ldo ASM_PMD_ENTRY*ASM_PMD_ENTRY_SIZE(%r5),%r4
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#else
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/* 2-level page table, so pmd == pgd */
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ldo ASM_PGD_ENTRY*ASM_PGD_ENTRY_SIZE(%r4),%r4
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#endif
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/* Fill in pmd with enough pte directories */
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load32 PA(pg0),%r1
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SHRREG %r1,PxD_VALUE_SHIFT,%r3
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ldo (PxD_FLAG_PRESENT+PxD_FLAG_VALID)(%r3),%r3
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ldi ASM_PT_INITIAL,%r1
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1:
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stw %r3,0(%r4)
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ldo (ASM_PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
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addib,> -1,%r1,1b
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#ifdef __LP64__
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ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
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#else
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ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
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#endif
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/* Now initialize the PTEs themselves */
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ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */
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load32 PA(pg0),%r1
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$pgt_fill_loop:
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STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1)
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ldo ASM_PAGE_SIZE(%r3),%r3
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bb,>= %r3,31-KERNEL_INITIAL_ORDER,$pgt_fill_loop
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nop
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/* Load the return address...er...crash 'n burn */
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copy %r0,%r2
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/* And the RFI Target address too */
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load32 start_kernel,%r11
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/* And the initial task pointer */
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load32 init_thread_union,%r6
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mtctl %r6,%cr30
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/* And the stack pointer too */
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ldo THREAD_SZ_ALGN(%r6),%sp
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/* And the interrupt stack */
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load32 interrupt_stack,%r6
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mtctl %r6,%cr31
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#ifdef CONFIG_SMP
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/* Set the smp rendevous address into page zero.
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** It would be safer to do this in init_smp_config() but
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** it's just way easier to deal with here because
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** of 64-bit function ptrs and the address is local to this file.
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*/
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load32 PA(smp_slave_stext),%r10
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stw %r10,0x10(%r0) /* MEM_RENDEZ */
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stw %r0,0x28(%r0) /* MEM_RENDEZ_HI - assume addr < 4GB */
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/* FALLTHROUGH */
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.procend
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/*
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** Code Common to both Monarch and Slave processors.
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** Entry:
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**
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** 1.1:
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** %r11 must contain RFI target address.
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** %r25/%r26 args to pass to target function
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** %r2 in case rfi target decides it didn't like something
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**
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** 2.0w:
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** %r3 PDCE_PROC address
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** %r11 RFI target address
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**
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** Caller must init: SR4-7, %sp, %r10, %cr24/25,
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*/
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common_stext:
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.proc
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.callinfo
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#else
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/* Clear PDC entry point - we won't use it */
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stw %r0,0x10(%r0) /* MEM_RENDEZ */
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stw %r0,0x28(%r0) /* MEM_RENDEZ_HI */
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#endif /*CONFIG_SMP*/
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#ifdef __LP64__
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tophys_r1 %sp
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/* Save the rfi target address */
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ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
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tophys_r1 %r10
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std %r11, TASK_PT_GR11(%r10)
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/* Switch to wide mode Superdome doesn't support narrow PDC
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** calls.
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*/
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1: mfia %rp /* clear upper part of pcoq */
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ldo 2f-1b(%rp),%rp
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depdi 0,31,32,%rp
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bv (%rp)
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ssm PSW_SM_W,%r0
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/* Set Wide mode as the "Default" (eg for traps)
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** First trap occurs *right* after (or part of) rfi for slave CPUs.
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** Someday, palo might not do this for the Monarch either.
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*/
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2:
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#define MEM_PDC_LO 0x388
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#define MEM_PDC_HI 0x35C
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ldw MEM_PDC_LO(%r0),%r3
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ldw MEM_PDC_HI(%r0),%r6
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depd %r6, 31, 32, %r3 /* move to upper word */
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ldo PDC_PSW(%r0),%arg0 /* 21 */
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ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
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ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */
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load32 PA(stext_pdc_ret), %rp
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bv (%r3)
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copy %r0,%arg3
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stext_pdc_ret:
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/* restore rfi target address*/
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ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
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tophys_r1 %r10
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ldd TASK_PT_GR11(%r10), %r11
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tovirt_r1 %sp
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#endif
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/* PARANOID: clear user scratch/user space SR's */
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mtsp %r0,%sr0
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mtsp %r0,%sr1
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mtsp %r0,%sr2
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mtsp %r0,%sr3
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/* Initialize Protection Registers */
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mtctl %r0,%cr8
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mtctl %r0,%cr9
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mtctl %r0,%cr12
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mtctl %r0,%cr13
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/* Prepare to RFI! Man all the cannons! */
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/* Initialize the global data pointer */
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loadgp
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/* Set up our interrupt table. HPMCs might not work after this!
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*
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* We need to install the correct iva for PA1.1 or PA2.0. The
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* following short sequence of instructions can determine this
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* (without being illegal on a PA1.1 machine).
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*/
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#ifndef __LP64__
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ldi 32,%r10
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mtctl %r10,%cr11
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.level 2.0
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mfctl,w %cr11,%r10
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.level 1.1
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comib,<>,n 0,%r10,$is_pa20
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ldil L%PA(fault_vector_11),%r10
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b $install_iva
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ldo R%PA(fault_vector_11)(%r10),%r10
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$is_pa20:
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.level LEVEL /* restore 1.1 || 2.0w */
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#endif /*!LP64*/
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load32 PA(fault_vector_20),%r10
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$install_iva:
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mtctl %r10,%cr14
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#ifdef __LP64__
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b aligned_rfi
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nop
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.align 256
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aligned_rfi:
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ssm 0,0
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nop /* 1 */
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nop /* 2 */
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nop /* 3 */
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nop /* 4 */
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nop /* 5 */
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nop /* 6 */
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nop /* 7 */
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nop /* 8 */
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#endif
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#ifdef __LP64__ /* move to psw.h? */
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#define PSW_BITS PSW_Q+PSW_I+PSW_D+PSW_P+PSW_R
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#else
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#define PSW_BITS PSW_SM_Q
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#endif
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$rfi:
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/* turn off troublesome PSW bits */
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rsm PSW_BITS,%r0
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/* kernel PSW:
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* - no interruptions except HPMC and TOC (which are handled by PDC)
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* - Q bit set (IODC / PDC interruptions)
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* - big-endian
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* - virtually mapped
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*/
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load32 KERNEL_PSW,%r10
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mtctl %r10,%ipsw
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/* Set the space pointers for the post-RFI world
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** Clear the two-level IIA Space Queue, effectively setting
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** Kernel space.
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*/
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mtctl %r0,%cr17 /* Clear IIASQ tail */
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mtctl %r0,%cr17 /* Clear IIASQ head */
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/* Load RFI target into PC queue */
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mtctl %r11,%cr18 /* IIAOQ head */
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ldo 4(%r11),%r11
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mtctl %r11,%cr18 /* IIAOQ tail */
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/* Jump to hyperspace */
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rfi
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nop
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.procend
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#ifdef CONFIG_SMP
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.import smp_init_current_idle_task,data
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.import smp_callin,code
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#ifndef __LP64__
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smp_callin_rtn:
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.proc
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.callinfo
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break 1,1 /* Break if returned from start_secondary */
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nop
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nop
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.procend
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#endif /*!LP64*/
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/***************************************************************************
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* smp_slave_stext is executed by all non-monarch Processors when the Monarch
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* pokes the slave CPUs in smp.c:smp_boot_cpus().
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*
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* Once here, registers values are initialized in order to branch to virtual
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* mode. Once all available/eligible CPUs are in virtual mode, all are
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* released and start out by executing their own idle task.
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*****************************************************************************/
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smp_slave_stext:
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.proc
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.callinfo
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/*
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** Initialize Space registers
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*/
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mtsp %r0,%sr4
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mtsp %r0,%sr5
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mtsp %r0,%sr6
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mtsp %r0,%sr7
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/* Initialize the SP - monarch sets up smp_init_current_idle_task */
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load32 PA(smp_init_current_idle_task),%sp
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LDREG 0(%sp),%sp /* load task address */
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tophys_r1 %sp
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LDREG TASK_THREAD_INFO(%sp),%sp
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mtctl %sp,%cr30 /* store in cr30 */
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ldo THREAD_SZ_ALGN(%sp),%sp
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/* point CPU to kernel page tables */
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load32 PA(swapper_pg_dir),%r4
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mtctl %r4,%cr24 /* Initialize kernel root pointer */
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mtctl %r4,%cr25 /* Initialize user root pointer */
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#ifdef __LP64__
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/* Setup PDCE_PROC entry */
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copy %arg0,%r3
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#else
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/* Load RFI *return* address in case smp_callin bails */
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load32 smp_callin_rtn,%r2
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#endif
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/* Load RFI target address. */
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load32 smp_callin,%r11
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/* ok...common code can handle the rest */
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b common_stext
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nop
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.procend
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#endif /* CONFIG_SMP */
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#ifndef __LP64__
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.data
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.align 4
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.export $global$,data
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.type $global$,@object
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.size $global$,4
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$global$:
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.word 0
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#endif /*!LP64*/
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