433 lines
12 KiB
C
433 lines
12 KiB
C
/*
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* OKI Semiconductor ML86V7667 video decoder driver
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*
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* Author: Vladimir Barinov <source@cogentembedded.com>
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* Copyright (C) 2013 Cogent Embedded, Inc.
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/videodev2.h>
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#include <media/v4l2-subdev.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ioctl.h>
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#include <media/v4l2-ctrls.h>
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#define DRV_NAME "ml86v7667"
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/* Subaddresses */
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#define MRA_REG 0x00 /* Mode Register A */
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#define MRC_REG 0x02 /* Mode Register C */
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#define LUMC_REG 0x0C /* Luminance Control */
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#define CLC_REG 0x10 /* Contrast level control */
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#define SSEPL_REG 0x11 /* Sync separation level */
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#define CHRCA_REG 0x12 /* Chrominance Control A */
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#define ACCC_REG 0x14 /* ACC Loop filter & Chrominance control */
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#define ACCRC_REG 0x15 /* ACC Reference level control */
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#define HUE_REG 0x16 /* Hue control */
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#define ADC2_REG 0x1F /* ADC Register 2 */
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#define PLLR1_REG 0x20 /* PLL Register 1 */
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#define STATUS_REG 0x2C /* STATUS Register */
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/* Mode Register A register bits */
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#define MRA_OUTPUT_MODE_MASK (3 << 6)
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#define MRA_ITUR_BT601 (1 << 6)
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#define MRA_ITUR_BT656 (0 << 6)
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#define MRA_INPUT_MODE_MASK (7 << 3)
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#define MRA_PAL_BT601 (4 << 3)
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#define MRA_NTSC_BT601 (0 << 3)
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#define MRA_REGISTER_MODE (1 << 0)
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/* Mode Register C register bits */
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#define MRC_AUTOSELECT (1 << 7)
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/* Luminance Control register bits */
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#define LUMC_ONOFF_SHIFT 7
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#define LUMC_ONOFF_MASK (1 << 7)
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/* Contrast level control register bits */
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#define CLC_CONTRAST_ONOFF (1 << 7)
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#define CLC_CONTRAST_MASK 0x0F
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/* Sync separation level register bits */
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#define SSEPL_LUMINANCE_ONOFF (1 << 7)
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#define SSEPL_LUMINANCE_MASK 0x7F
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/* Chrominance Control A register bits */
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#define CHRCA_MODE_SHIFT 6
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#define CHRCA_MODE_MASK (1 << 6)
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/* ACC Loop filter & Chrominance control register bits */
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#define ACCC_CHROMA_CR_SHIFT 3
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#define ACCC_CHROMA_CR_MASK (7 << 3)
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#define ACCC_CHROMA_CB_SHIFT 0
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#define ACCC_CHROMA_CB_MASK (7 << 0)
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/* ACC Reference level control register bits */
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#define ACCRC_CHROMA_MASK 0xfc
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#define ACCRC_CHROMA_SHIFT 2
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/* ADC Register 2 register bits */
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#define ADC2_CLAMP_VOLTAGE_MASK (7 << 1)
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#define ADC2_CLAMP_VOLTAGE(n) ((n & 7) << 1)
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/* PLL Register 1 register bits */
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#define PLLR1_FIXED_CLOCK (1 << 7)
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/* STATUS Register register bits */
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#define STATUS_HLOCK_DETECT (1 << 3)
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#define STATUS_NTSCPAL (1 << 2)
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struct ml86v7667_priv {
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struct v4l2_subdev sd;
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struct v4l2_ctrl_handler hdl;
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v4l2_std_id std;
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};
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static inline struct ml86v7667_priv *to_ml86v7667(struct v4l2_subdev *subdev)
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{
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return container_of(subdev, struct ml86v7667_priv, sd);
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}
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static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
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{
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return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd;
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}
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static int ml86v7667_mask_set(struct i2c_client *client, const u8 reg,
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const u8 mask, const u8 data)
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{
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int val = i2c_smbus_read_byte_data(client, reg);
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if (val < 0)
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return val;
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val = (val & ~mask) | (data & mask);
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return i2c_smbus_write_byte_data(client, reg, val);
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}
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static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct v4l2_subdev *sd = to_sd(ctrl);
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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int ret = -EINVAL;
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switch (ctrl->id) {
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case V4L2_CID_BRIGHTNESS:
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ret = ml86v7667_mask_set(client, SSEPL_REG,
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SSEPL_LUMINANCE_MASK, ctrl->val);
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break;
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case V4L2_CID_CONTRAST:
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ret = ml86v7667_mask_set(client, CLC_REG,
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CLC_CONTRAST_MASK, ctrl->val);
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break;
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case V4L2_CID_CHROMA_GAIN:
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ret = ml86v7667_mask_set(client, ACCRC_REG, ACCRC_CHROMA_MASK,
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ctrl->val << ACCRC_CHROMA_SHIFT);
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break;
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case V4L2_CID_HUE:
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ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val);
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break;
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case V4L2_CID_RED_BALANCE:
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ret = ml86v7667_mask_set(client, ACCC_REG,
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ACCC_CHROMA_CR_MASK,
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ctrl->val << ACCC_CHROMA_CR_SHIFT);
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break;
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case V4L2_CID_BLUE_BALANCE:
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ret = ml86v7667_mask_set(client, ACCC_REG,
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ACCC_CHROMA_CB_MASK,
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ctrl->val << ACCC_CHROMA_CB_SHIFT);
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break;
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case V4L2_CID_SHARPNESS:
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ret = ml86v7667_mask_set(client, LUMC_REG,
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LUMC_ONOFF_MASK,
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ctrl->val << LUMC_ONOFF_SHIFT);
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break;
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case V4L2_CID_COLOR_KILLER:
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ret = ml86v7667_mask_set(client, CHRCA_REG,
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CHRCA_MODE_MASK,
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ctrl->val << CHRCA_MODE_SHIFT);
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break;
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}
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return ret;
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}
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static int ml86v7667_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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int status;
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status = i2c_smbus_read_byte_data(client, STATUS_REG);
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if (status < 0)
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return status;
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if (status & STATUS_HLOCK_DETECT)
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*std &= status & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
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else
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*std = V4L2_STD_UNKNOWN;
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return 0;
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}
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static int ml86v7667_g_input_status(struct v4l2_subdev *sd, u32 *status)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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int status_reg;
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status_reg = i2c_smbus_read_byte_data(client, STATUS_REG);
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if (status_reg < 0)
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return status_reg;
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*status = status_reg & STATUS_HLOCK_DETECT ? 0 : V4L2_IN_ST_NO_SIGNAL;
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return 0;
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}
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static int ml86v7667_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
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u32 *code)
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{
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if (index > 0)
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return -EINVAL;
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*code = MEDIA_BUS_FMT_YUYV8_2X8;
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return 0;
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}
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static int ml86v7667_mbus_fmt(struct v4l2_subdev *sd,
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struct v4l2_mbus_framefmt *fmt)
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{
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struct ml86v7667_priv *priv = to_ml86v7667(sd);
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fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
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fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
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/* The top field is always transferred first by the chip */
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fmt->field = V4L2_FIELD_INTERLACED_TB;
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fmt->width = 720;
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fmt->height = priv->std & V4L2_STD_525_60 ? 480 : 576;
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return 0;
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}
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static int ml86v7667_g_mbus_config(struct v4l2_subdev *sd,
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struct v4l2_mbus_config *cfg)
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{
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cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
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V4L2_MBUS_DATA_ACTIVE_HIGH;
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cfg->type = V4L2_MBUS_BT656;
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return 0;
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}
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static int ml86v7667_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
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{
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struct ml86v7667_priv *priv = to_ml86v7667(sd);
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struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
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int ret;
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u8 mode;
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/* PAL/NTSC ITU-R BT.601 input mode */
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mode = std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
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ret = ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, mode);
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if (ret < 0)
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return ret;
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priv->std = std;
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return 0;
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}
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#ifdef CONFIG_VIDEO_ADV_DEBUG
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static int ml86v7667_g_register(struct v4l2_subdev *sd,
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struct v4l2_dbg_register *reg)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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int ret;
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ret = i2c_smbus_read_byte_data(client, (u8)reg->reg);
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if (ret < 0)
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return ret;
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reg->val = ret;
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reg->size = sizeof(u8);
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return 0;
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}
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static int ml86v7667_s_register(struct v4l2_subdev *sd,
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const struct v4l2_dbg_register *reg)
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{
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struct i2c_client *client = v4l2_get_subdevdata(sd);
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return i2c_smbus_write_byte_data(client, (u8)reg->reg, (u8)reg->val);
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}
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#endif
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static const struct v4l2_ctrl_ops ml86v7667_ctrl_ops = {
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.s_ctrl = ml86v7667_s_ctrl,
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};
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static struct v4l2_subdev_video_ops ml86v7667_subdev_video_ops = {
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.s_std = ml86v7667_s_std,
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.querystd = ml86v7667_querystd,
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.g_input_status = ml86v7667_g_input_status,
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.enum_mbus_fmt = ml86v7667_enum_mbus_fmt,
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.try_mbus_fmt = ml86v7667_mbus_fmt,
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.g_mbus_fmt = ml86v7667_mbus_fmt,
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.s_mbus_fmt = ml86v7667_mbus_fmt,
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.g_mbus_config = ml86v7667_g_mbus_config,
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};
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static struct v4l2_subdev_core_ops ml86v7667_subdev_core_ops = {
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#ifdef CONFIG_VIDEO_ADV_DEBUG
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.g_register = ml86v7667_g_register,
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.s_register = ml86v7667_s_register,
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#endif
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};
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static struct v4l2_subdev_ops ml86v7667_subdev_ops = {
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.core = &ml86v7667_subdev_core_ops,
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.video = &ml86v7667_subdev_video_ops,
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};
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static int ml86v7667_init(struct ml86v7667_priv *priv)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
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int val;
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int ret;
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/* BT.656-4 output mode, register mode */
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ret = ml86v7667_mask_set(client, MRA_REG,
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MRA_OUTPUT_MODE_MASK | MRA_REGISTER_MODE,
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MRA_ITUR_BT656 | MRA_REGISTER_MODE);
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/* PLL circuit fixed clock, 32MHz */
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ret |= ml86v7667_mask_set(client, PLLR1_REG, PLLR1_FIXED_CLOCK,
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PLLR1_FIXED_CLOCK);
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/* ADC2 clamping voltage maximum */
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ret |= ml86v7667_mask_set(client, ADC2_REG, ADC2_CLAMP_VOLTAGE_MASK,
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ADC2_CLAMP_VOLTAGE(7));
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/* enable luminance function */
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ret |= ml86v7667_mask_set(client, SSEPL_REG, SSEPL_LUMINANCE_ONOFF,
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SSEPL_LUMINANCE_ONOFF);
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/* enable contrast function */
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ret |= ml86v7667_mask_set(client, CLC_REG, CLC_CONTRAST_ONOFF, 0);
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/*
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* PAL/NTSC autodetection is enabled after reset,
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* set the autodetected std in manual std mode and
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* disable autodetection
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*/
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val = i2c_smbus_read_byte_data(client, STATUS_REG);
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if (val < 0)
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return val;
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priv->std = val & STATUS_NTSCPAL ? V4L2_STD_625_50 : V4L2_STD_525_60;
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ret |= ml86v7667_mask_set(client, MRC_REG, MRC_AUTOSELECT, 0);
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val = priv->std & V4L2_STD_525_60 ? MRA_NTSC_BT601 : MRA_PAL_BT601;
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ret |= ml86v7667_mask_set(client, MRA_REG, MRA_INPUT_MODE_MASK, val);
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return ret;
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}
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static int ml86v7667_probe(struct i2c_client *client,
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const struct i2c_device_id *did)
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{
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struct ml86v7667_priv *priv;
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int ret;
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if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
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return -EIO;
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priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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v4l2_i2c_subdev_init(&priv->sd, client, &ml86v7667_subdev_ops);
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v4l2_ctrl_handler_init(&priv->hdl, 8);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_BRIGHTNESS, -64, 63, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_CONTRAST, -8, 7, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_CHROMA_GAIN, -32, 31, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_HUE, -128, 127, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_RED_BALANCE, -4, 3, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_BLUE_BALANCE, -4, 3, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_SHARPNESS, 0, 1, 1, 0);
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v4l2_ctrl_new_std(&priv->hdl, &ml86v7667_ctrl_ops,
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V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
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priv->sd.ctrl_handler = &priv->hdl;
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ret = priv->hdl.error;
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if (ret)
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goto cleanup;
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v4l2_ctrl_handler_setup(&priv->hdl);
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ret = ml86v7667_init(priv);
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if (ret)
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goto cleanup;
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v4l_info(client, "chip found @ 0x%02x (%s)\n",
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client->addr, client->adapter->name);
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return 0;
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cleanup:
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v4l2_ctrl_handler_free(&priv->hdl);
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v4l2_device_unregister_subdev(&priv->sd);
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v4l_err(client, "failed to probe @ 0x%02x (%s)\n",
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client->addr, client->adapter->name);
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return ret;
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}
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static int ml86v7667_remove(struct i2c_client *client)
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{
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struct v4l2_subdev *sd = i2c_get_clientdata(client);
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struct ml86v7667_priv *priv = to_ml86v7667(sd);
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v4l2_ctrl_handler_free(&priv->hdl);
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v4l2_device_unregister_subdev(&priv->sd);
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return 0;
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}
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static const struct i2c_device_id ml86v7667_id[] = {
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{DRV_NAME, 0},
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{},
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};
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MODULE_DEVICE_TABLE(i2c, ml86v7667_id);
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static struct i2c_driver ml86v7667_i2c_driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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.probe = ml86v7667_probe,
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.remove = ml86v7667_remove,
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.id_table = ml86v7667_id,
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};
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module_i2c_driver(ml86v7667_i2c_driver);
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MODULE_DESCRIPTION("OKI Semiconductor ML86V7667 video decoder driver");
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MODULE_AUTHOR("Vladimir Barinov");
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MODULE_LICENSE("GPL");
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