573 lines
15 KiB
C
573 lines
15 KiB
C
/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <asm/iosf_mbi.h>
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#include "i915_drv.h"
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#include "intel_sideband.h"
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/*
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* IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
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* VLV_VLV2_PUNIT_HAS_0.8.docx
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*/
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/* Standard MMIO read, non-posted */
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#define SB_MRD_NP 0x00
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/* Standard MMIO write, non-posted */
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#define SB_MWR_NP 0x01
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/* Private register read, double-word addressing, non-posted */
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#define SB_CRRDDA_NP 0x06
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/* Private register write, double-word addressing, non-posted */
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#define SB_CRWRDA_NP 0x07
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static void ping(void *info)
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{
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}
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static void __vlv_punit_get(struct drm_i915_private *i915)
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{
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iosf_mbi_punit_acquire();
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/*
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* Prevent the cpu from sleeping while we use this sideband, otherwise
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* the punit may cause a machine hang. The issue appears to be isolated
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* with changing the power state of the CPU package while changing
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* the power state via the punit, and we have only observed it
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* reliably on 4-core Baytail systems suggesting the issue is in the
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* power delivery mechanism and likely to be be board/function
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* specific. Hence we presume the workaround needs only be applied
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* to the Valleyview P-unit and not all sideband communications.
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*/
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if (IS_VALLEYVIEW(i915)) {
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cpu_latency_qos_update_request(&i915->sb_qos, 0);
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on_each_cpu(ping, NULL, 1);
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}
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}
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static void __vlv_punit_put(struct drm_i915_private *i915)
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{
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if (IS_VALLEYVIEW(i915))
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cpu_latency_qos_update_request(&i915->sb_qos,
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PM_QOS_DEFAULT_VALUE);
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iosf_mbi_punit_release();
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}
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void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
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{
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if (ports & BIT(VLV_IOSF_SB_PUNIT))
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__vlv_punit_get(i915);
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mutex_lock(&i915->sb_lock);
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}
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void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
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{
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mutex_unlock(&i915->sb_lock);
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if (ports & BIT(VLV_IOSF_SB_PUNIT))
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__vlv_punit_put(i915);
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}
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static int vlv_sideband_rw(struct drm_i915_private *i915,
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u32 devfn, u32 port, u32 opcode,
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u32 addr, u32 *val)
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{
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struct intel_uncore *uncore = &i915->uncore;
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const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
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int err;
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lockdep_assert_held(&i915->sb_lock);
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if (port == IOSF_PORT_PUNIT)
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iosf_mbi_assert_punit_acquired();
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/* Flush the previous comms, just in case it failed last time. */
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if (intel_wait_for_register(uncore,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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5)) {
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drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
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is_read ? "read" : "write");
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return -EAGAIN;
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}
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preempt_disable();
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intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
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intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
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intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
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(devfn << IOSF_DEVFN_SHIFT) |
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(opcode << IOSF_OPCODE_SHIFT) |
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(port << IOSF_PORT_SHIFT) |
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(0xf << IOSF_BYTE_ENABLES_SHIFT) |
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(0 << IOSF_BAR_SHIFT) |
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IOSF_SB_BUSY);
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if (__intel_wait_for_register_fw(uncore,
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VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
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10000, 0, NULL) == 0) {
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if (is_read)
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*val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
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err = 0;
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} else {
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drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
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is_read ? "read" : "write");
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err = -ETIMEDOUT;
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}
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preempt_enable();
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return err;
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}
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u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRRDDA_NP, addr, &val);
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return val;
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}
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int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
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{
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return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
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SB_CRWRDA_NP, addr, &val);
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}
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u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
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SB_CRRDDA_NP, addr, &val);
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return val;
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}
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u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_iosf_sb_write(struct drm_i915_private *i915,
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u8 port, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
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SB_CRWRDA_NP, reg, &val);
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}
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u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRRDDA_NP, reg, &val);
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return val;
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}
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void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
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SB_CRWRDA_NP, reg, &val);
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}
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static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
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{
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/*
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* IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
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* IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
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*/
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if (IS_CHERRYVIEW(i915))
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return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO;
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else
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return IOSF_PORT_DPIO;
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}
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u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
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{
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u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
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u32 val = 0;
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vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
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/*
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* FIXME: There might be some registers where all 1's is a valid value,
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* so ideally we should check the register offset instead...
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*/
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drm_WARN(&i915->drm, val == 0xffffffff,
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"DPIO read pipe %c reg 0x%x == 0x%x\n",
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pipe_name(pipe), reg, val);
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return val;
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}
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void vlv_dpio_write(struct drm_i915_private *i915,
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enum pipe pipe, int reg, u32 val)
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{
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u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
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vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
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}
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u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
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{
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u32 val = 0;
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vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
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reg, &val);
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return val;
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}
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void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
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{
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vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
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reg, &val);
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}
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/* SBI access */
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static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
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enum intel_sbi_destination destination,
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u32 *val, bool is_read)
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{
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struct intel_uncore *uncore = &i915->uncore;
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u32 cmd;
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lockdep_assert_held(&i915->sb_lock);
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if (intel_wait_for_register_fw(uncore,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100)) {
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drm_err(&i915->drm,
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"timeout waiting for SBI to become ready\n");
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return -EBUSY;
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}
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intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
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intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
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if (destination == SBI_ICLK)
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cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
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else
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cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
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if (!is_read)
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cmd |= BIT(8);
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intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
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if (__intel_wait_for_register_fw(uncore,
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SBI_CTL_STAT, SBI_BUSY, 0,
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100, 100, &cmd)) {
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drm_err(&i915->drm,
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"timeout waiting for SBI to complete read\n");
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return -ETIMEDOUT;
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}
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if (cmd & SBI_RESPONSE_FAIL) {
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drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
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return -ENXIO;
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}
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if (is_read)
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*val = intel_uncore_read_fw(uncore, SBI_DATA);
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return 0;
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}
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u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
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enum intel_sbi_destination destination)
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{
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u32 result = 0;
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intel_sbi_rw(i915, reg, destination, &result, true);
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return result;
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}
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void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
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enum intel_sbi_destination destination)
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{
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intel_sbi_rw(i915, reg, destination, &value, false);
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}
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static int gen6_check_mailbox_status(u32 mbox)
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{
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switch (mbox & GEN6_PCODE_ERROR_MASK) {
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case GEN6_PCODE_SUCCESS:
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return 0;
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case GEN6_PCODE_UNIMPLEMENTED_CMD:
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return -ENODEV;
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case GEN6_PCODE_ILLEGAL_CMD:
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return -ENXIO;
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case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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return -EOVERFLOW;
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case GEN6_PCODE_TIMEOUT:
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return -ETIMEDOUT;
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default:
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MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
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return 0;
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}
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}
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static int gen7_check_mailbox_status(u32 mbox)
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{
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switch (mbox & GEN6_PCODE_ERROR_MASK) {
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case GEN6_PCODE_SUCCESS:
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return 0;
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case GEN6_PCODE_ILLEGAL_CMD:
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return -ENXIO;
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case GEN7_PCODE_TIMEOUT:
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return -ETIMEDOUT;
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case GEN7_PCODE_ILLEGAL_DATA:
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return -EINVAL;
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case GEN11_PCODE_ILLEGAL_SUBCOMMAND:
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return -ENXIO;
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case GEN11_PCODE_LOCKED:
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return -EBUSY;
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case GEN11_PCODE_REJECTED:
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return -EACCES;
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case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
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return -EOVERFLOW;
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default:
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MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
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return 0;
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}
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}
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static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
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u32 mbox, u32 *val, u32 *val1,
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int fast_timeout_us,
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int slow_timeout_ms,
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bool is_read)
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{
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struct intel_uncore *uncore = &i915->uncore;
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lockdep_assert_held(&i915->sb_lock);
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/*
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* GEN6_PCODE_* are outside of the forcewake domain, we can
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* use te fw I915_READ variants to reduce the amount of work
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* required when reading/writing.
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*/
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if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
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return -EAGAIN;
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intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
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intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
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intel_uncore_write_fw(uncore,
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GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
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if (__intel_wait_for_register_fw(uncore,
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GEN6_PCODE_MAILBOX,
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GEN6_PCODE_READY, 0,
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fast_timeout_us,
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slow_timeout_ms,
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&mbox))
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return -ETIMEDOUT;
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if (is_read)
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*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
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if (is_read && val1)
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*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
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if (INTEL_GEN(i915) > 6)
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return gen7_check_mailbox_status(mbox);
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else
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return gen6_check_mailbox_status(mbox);
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}
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int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
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u32 *val, u32 *val1)
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{
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int err;
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mutex_lock(&i915->sb_lock);
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err = __sandybridge_pcode_rw(i915, mbox, val, val1,
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500, 20,
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true);
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mutex_unlock(&i915->sb_lock);
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if (err) {
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drm_dbg(&i915->drm,
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"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
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mbox, __builtin_return_address(0), err);
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}
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return err;
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}
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int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
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u32 mbox, u32 val,
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int fast_timeout_us,
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int slow_timeout_ms)
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{
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int err;
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mutex_lock(&i915->sb_lock);
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err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
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fast_timeout_us, slow_timeout_ms,
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false);
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mutex_unlock(&i915->sb_lock);
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if (err) {
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drm_dbg(&i915->drm,
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"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
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val, mbox, __builtin_return_address(0), err);
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}
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return err;
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}
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static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
|
|
u32 request, u32 reply_mask, u32 reply,
|
|
u32 *status)
|
|
{
|
|
*status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
|
|
500, 0,
|
|
true);
|
|
|
|
return *status || ((request & reply_mask) == reply);
|
|
}
|
|
|
|
/**
|
|
* skl_pcode_request - send PCODE request until acknowledgment
|
|
* @i915: device private
|
|
* @mbox: PCODE mailbox ID the request is targeted for
|
|
* @request: request ID
|
|
* @reply_mask: mask used to check for request acknowledgment
|
|
* @reply: value used to check for request acknowledgment
|
|
* @timeout_base_ms: timeout for polling with preemption enabled
|
|
*
|
|
* Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
|
|
* reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
|
|
* The request is acknowledged once the PCODE reply dword equals @reply after
|
|
* applying @reply_mask. Polling is first attempted with preemption enabled
|
|
* for @timeout_base_ms and if this times out for another 50 ms with
|
|
* preemption disabled.
|
|
*
|
|
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
|
|
* other error as reported by PCODE.
|
|
*/
|
|
int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
|
|
u32 reply_mask, u32 reply, int timeout_base_ms)
|
|
{
|
|
u32 status;
|
|
int ret;
|
|
|
|
mutex_lock(&i915->sb_lock);
|
|
|
|
#define COND \
|
|
skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
|
|
|
|
/*
|
|
* Prime the PCODE by doing a request first. Normally it guarantees
|
|
* that a subsequent request, at most @timeout_base_ms later, succeeds.
|
|
* _wait_for() doesn't guarantee when its passed condition is evaluated
|
|
* first, so send the first request explicitly.
|
|
*/
|
|
if (COND) {
|
|
ret = 0;
|
|
goto out;
|
|
}
|
|
ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
|
|
if (!ret)
|
|
goto out;
|
|
|
|
/*
|
|
* The above can time out if the number of requests was low (2 in the
|
|
* worst case) _and_ PCODE was busy for some reason even after a
|
|
* (queued) request and @timeout_base_ms delay. As a workaround retry
|
|
* the poll with preemption disabled to maximize the number of
|
|
* requests. Increase the timeout from @timeout_base_ms to 50ms to
|
|
* account for interrupts that could reduce the number of these
|
|
* requests, and for any quirks of the PCODE firmware that delays
|
|
* the request completion.
|
|
*/
|
|
drm_dbg_kms(&i915->drm,
|
|
"PCODE timeout, retrying with preemption disabled\n");
|
|
drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
|
|
preempt_disable();
|
|
ret = wait_for_atomic(COND, 50);
|
|
preempt_enable();
|
|
|
|
out:
|
|
mutex_unlock(&i915->sb_lock);
|
|
return ret ? ret : status;
|
|
#undef COND
|
|
}
|
|
|
|
void intel_pcode_init(struct drm_i915_private *i915)
|
|
{
|
|
int ret;
|
|
|
|
if (!IS_DGFX(i915))
|
|
return;
|
|
|
|
ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
|
|
DG1_UNCORE_GET_INIT_STATUS,
|
|
DG1_UNCORE_INIT_STATUS_COMPLETE,
|
|
DG1_UNCORE_INIT_STATUS_COMPLETE, 50);
|
|
if (ret)
|
|
drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
|
|
}
|