487 lines
14 KiB
C
487 lines
14 KiB
C
/*
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* Copyright (c) 2011 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/dcbnl.h>
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#include <linux/math64.h>
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#include "mlx4_en.h"
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#include "fw_qos.h"
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/* Definitions for QCN
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*/
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struct mlx4_congestion_control_mb_prio_802_1_qau_params {
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__be32 modify_enable_high;
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__be32 modify_enable_low;
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__be32 reserved1;
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__be32 extended_enable;
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__be32 rppp_max_rps;
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__be32 rpg_time_reset;
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__be32 rpg_byte_reset;
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__be32 rpg_threshold;
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__be32 rpg_max_rate;
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__be32 rpg_ai_rate;
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__be32 rpg_hai_rate;
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__be32 rpg_gd;
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__be32 rpg_min_dec_fac;
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__be32 rpg_min_rate;
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__be32 max_time_rise;
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__be32 max_byte_rise;
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__be32 max_qdelta;
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__be32 min_qoffset;
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__be32 gd_coefficient;
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__be32 reserved2[5];
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__be32 cp_sample_base;
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__be32 reserved3[39];
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};
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struct mlx4_congestion_control_mb_prio_802_1_qau_statistics {
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__be64 rppp_rp_centiseconds;
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__be32 reserved1;
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__be32 ignored_cnm;
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__be32 rppp_created_rps;
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__be32 estimated_total_rate;
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__be32 max_active_rate_limiter_index;
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__be32 dropped_cnms_busy_fw;
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__be32 reserved2;
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__be32 cnms_handled_successfully;
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__be32 min_total_limiters_rate;
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__be32 max_total_limiters_rate;
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__be32 reserved3[4];
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};
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static int mlx4_en_dcbnl_ieee_getets(struct net_device *dev,
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struct ieee_ets *ets)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct ieee_ets *my_ets = &priv->ets;
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/* No IEEE PFC settings available */
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if (!my_ets)
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return -EINVAL;
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ets->ets_cap = IEEE_8021QAZ_MAX_TCS;
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ets->cbs = my_ets->cbs;
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memcpy(ets->tc_tx_bw, my_ets->tc_tx_bw, sizeof(ets->tc_tx_bw));
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memcpy(ets->tc_tsa, my_ets->tc_tsa, sizeof(ets->tc_tsa));
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memcpy(ets->prio_tc, my_ets->prio_tc, sizeof(ets->prio_tc));
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return 0;
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}
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static int mlx4_en_ets_validate(struct mlx4_en_priv *priv, struct ieee_ets *ets)
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{
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int i;
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int total_ets_bw = 0;
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int has_ets_tc = 0;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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if (ets->prio_tc[i] >= MLX4_EN_NUM_UP) {
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en_err(priv, "Bad priority in UP <=> TC mapping. TC: %d, UP: %d\n",
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i, ets->prio_tc[i]);
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return -EINVAL;
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}
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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break;
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case IEEE_8021QAZ_TSA_ETS:
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has_ets_tc = 1;
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total_ets_bw += ets->tc_tx_bw[i];
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break;
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default:
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en_err(priv, "TC[%d]: Not supported TSA: %d\n",
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i, ets->tc_tsa[i]);
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return -ENOTSUPP;
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}
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}
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if (has_ets_tc && total_ets_bw != MLX4_EN_BW_MAX) {
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en_err(priv, "Bad ETS BW sum: %d. Should be exactly 100%%\n",
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total_ets_bw);
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return -EINVAL;
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}
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return 0;
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}
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static int mlx4_en_config_port_scheduler(struct mlx4_en_priv *priv,
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struct ieee_ets *ets, u16 *ratelimit)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int num_strict = 0;
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int i;
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__u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS] = { 0 };
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__u8 pg[IEEE_8021QAZ_MAX_TCS] = { 0 };
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ets = ets ?: &priv->ets;
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ratelimit = ratelimit ?: priv->maxrate;
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/* higher TC means higher priority => lower pg */
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for (i = IEEE_8021QAZ_MAX_TCS - 1; i >= 0; i--) {
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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pg[i] = num_strict++;
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tc_tx_bw[i] = MLX4_EN_BW_MAX;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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pg[i] = MLX4_EN_TC_ETS;
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tc_tx_bw[i] = ets->tc_tx_bw[i] ?: MLX4_EN_BW_MIN;
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break;
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}
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}
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return mlx4_SET_PORT_SCHEDULER(mdev->dev, priv->port, tc_tx_bw, pg,
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ratelimit);
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}
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static int
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mlx4_en_dcbnl_ieee_setets(struct net_device *dev, struct ieee_ets *ets)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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err = mlx4_en_ets_validate(priv, ets);
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if (err)
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return err;
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err = mlx4_SET_PORT_PRIO2TC(mdev->dev, priv->port, ets->prio_tc);
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if (err)
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return err;
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err = mlx4_en_config_port_scheduler(priv, ets, NULL);
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if (err)
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return err;
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memcpy(&priv->ets, ets, sizeof(priv->ets));
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_getpfc(struct net_device *dev,
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struct ieee_pfc *pfc)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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pfc->pfc_cap = IEEE_8021QAZ_MAX_TCS;
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pfc->pfc_en = priv->prof->tx_ppp;
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_setpfc(struct net_device *dev,
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struct ieee_pfc *pfc)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_en_port_profile *prof = priv->prof;
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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en_dbg(DRV, priv, "cap: 0x%x en: 0x%x mbc: 0x%x delay: %d\n",
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pfc->pfc_cap,
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pfc->pfc_en,
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pfc->mbc,
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pfc->delay);
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prof->rx_pause = !pfc->pfc_en;
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prof->tx_pause = !pfc->pfc_en;
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prof->rx_ppp = pfc->pfc_en;
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prof->tx_ppp = pfc->pfc_en;
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err = mlx4_SET_PORT_general(mdev->dev, priv->port,
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priv->rx_skb_size + ETH_FCS_LEN,
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prof->tx_pause,
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prof->tx_ppp,
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prof->rx_pause,
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prof->rx_ppp);
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if (err)
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en_err(priv, "Failed setting pause params\n");
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else
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mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
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prof->rx_ppp, prof->rx_pause,
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prof->tx_ppp, prof->tx_pause);
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return err;
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}
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static u8 mlx4_en_dcbnl_getdcbx(struct net_device *dev)
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{
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return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
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}
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static u8 mlx4_en_dcbnl_setdcbx(struct net_device *dev, u8 mode)
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{
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if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
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(mode & DCB_CAP_DCBX_VER_CEE) ||
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!(mode & DCB_CAP_DCBX_VER_IEEE) ||
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!(mode & DCB_CAP_DCBX_HOST))
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return 1;
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return 0;
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}
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#define MLX4_RATELIMIT_UNITS_IN_KB 100000 /* rate-limit HW unit in Kbps */
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static int mlx4_en_dcbnl_ieee_getmaxrate(struct net_device *dev,
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struct ieee_maxrate *maxrate)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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int i;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
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maxrate->tc_maxrate[i] =
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priv->maxrate[i] * MLX4_RATELIMIT_UNITS_IN_KB;
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_setmaxrate(struct net_device *dev,
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struct ieee_maxrate *maxrate)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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u16 tmp[IEEE_8021QAZ_MAX_TCS];
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int i, err;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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/* Convert from Kbps into HW units, rounding result up.
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* Setting to 0, means unlimited BW.
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*/
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tmp[i] = div_u64(maxrate->tc_maxrate[i] +
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MLX4_RATELIMIT_UNITS_IN_KB - 1,
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MLX4_RATELIMIT_UNITS_IN_KB);
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}
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err = mlx4_en_config_port_scheduler(priv, NULL, tmp);
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if (err)
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return err;
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memcpy(priv->maxrate, tmp, sizeof(priv->maxrate));
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return 0;
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}
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#define RPG_ENABLE_BIT 31
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#define CN_TAG_BIT 30
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static int mlx4_en_dcbnl_ieee_getqcn(struct net_device *dev,
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struct ieee_qcn *qcn)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
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struct mlx4_cmd_mailbox *mailbox_out = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_out = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_out))
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return -ENOMEM;
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hw_qcn =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_params *)
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mailbox_out->buf;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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inmod = priv->port | ((1 << i) << 8) |
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(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
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err = mlx4_cmd_box(priv->mdev->dev, mailbox_in_dma,
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mailbox_out->dma,
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inmod, MLX4_CONGESTION_CONTROL_GET_PARAMS,
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MLX4_CMD_CONGESTION_CTRL_OPCODE,
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MLX4_CMD_TIME_CLASS_C,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return err;
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}
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qcn->rpg_enable[i] =
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be32_to_cpu(hw_qcn->extended_enable) >> RPG_ENABLE_BIT;
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qcn->rppp_max_rps[i] =
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be32_to_cpu(hw_qcn->rppp_max_rps);
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qcn->rpg_time_reset[i] =
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be32_to_cpu(hw_qcn->rpg_time_reset);
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qcn->rpg_byte_reset[i] =
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be32_to_cpu(hw_qcn->rpg_byte_reset);
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qcn->rpg_threshold[i] =
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be32_to_cpu(hw_qcn->rpg_threshold);
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qcn->rpg_max_rate[i] =
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be32_to_cpu(hw_qcn->rpg_max_rate);
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qcn->rpg_ai_rate[i] =
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be32_to_cpu(hw_qcn->rpg_ai_rate);
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qcn->rpg_hai_rate[i] =
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be32_to_cpu(hw_qcn->rpg_hai_rate);
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qcn->rpg_gd[i] =
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be32_to_cpu(hw_qcn->rpg_gd);
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qcn->rpg_min_dec_fac[i] =
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be32_to_cpu(hw_qcn->rpg_min_dec_fac);
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qcn->rpg_min_rate[i] =
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be32_to_cpu(hw_qcn->rpg_min_rate);
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qcn->cndd_state_machine[i] =
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priv->cndd_state[i];
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}
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_setqcn(struct net_device *dev,
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struct ieee_qcn *qcn)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_params *hw_qcn;
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struct mlx4_cmd_mailbox *mailbox_in = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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#define MODIFY_ENABLE_HIGH_MASK 0xc0000000
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#define MODIFY_ENABLE_LOW_MASK 0xffc00000
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_in = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_in))
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return -ENOMEM;
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mailbox_in_dma = mailbox_in->dma;
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hw_qcn =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_params *)mailbox_in->buf;
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for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
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inmod = priv->port | ((1 << i) << 8) |
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(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
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/* Before updating QCN parameter,
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* need to set it's modify enable bit to 1
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*/
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hw_qcn->modify_enable_high = cpu_to_be32(
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MODIFY_ENABLE_HIGH_MASK);
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hw_qcn->modify_enable_low = cpu_to_be32(MODIFY_ENABLE_LOW_MASK);
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hw_qcn->extended_enable = cpu_to_be32(qcn->rpg_enable[i] << RPG_ENABLE_BIT);
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hw_qcn->rppp_max_rps = cpu_to_be32(qcn->rppp_max_rps[i]);
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hw_qcn->rpg_time_reset = cpu_to_be32(qcn->rpg_time_reset[i]);
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hw_qcn->rpg_byte_reset = cpu_to_be32(qcn->rpg_byte_reset[i]);
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hw_qcn->rpg_threshold = cpu_to_be32(qcn->rpg_threshold[i]);
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hw_qcn->rpg_max_rate = cpu_to_be32(qcn->rpg_max_rate[i]);
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hw_qcn->rpg_ai_rate = cpu_to_be32(qcn->rpg_ai_rate[i]);
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hw_qcn->rpg_hai_rate = cpu_to_be32(qcn->rpg_hai_rate[i]);
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hw_qcn->rpg_gd = cpu_to_be32(qcn->rpg_gd[i]);
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hw_qcn->rpg_min_dec_fac = cpu_to_be32(qcn->rpg_min_dec_fac[i]);
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hw_qcn->rpg_min_rate = cpu_to_be32(qcn->rpg_min_rate[i]);
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priv->cndd_state[i] = qcn->cndd_state_machine[i];
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if (qcn->cndd_state_machine[i] == DCB_CNDD_INTERIOR_READY)
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hw_qcn->extended_enable |= cpu_to_be32(1 << CN_TAG_BIT);
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err = mlx4_cmd(priv->mdev->dev, mailbox_in_dma, inmod,
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MLX4_CONGESTION_CONTROL_SET_PARAMS,
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MLX4_CMD_CONGESTION_CTRL_OPCODE,
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MLX4_CMD_TIME_CLASS_C,
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MLX4_CMD_NATIVE);
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if (err) {
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_in);
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return err;
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}
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}
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mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_in);
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return 0;
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}
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static int mlx4_en_dcbnl_ieee_getqcnstats(struct net_device *dev,
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struct ieee_qcn_stats *qcn_stats)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_congestion_control_mb_prio_802_1_qau_statistics *hw_qcn_stats;
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struct mlx4_cmd_mailbox *mailbox_out = NULL;
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u64 mailbox_in_dma = 0;
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u32 inmod = 0;
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int i, err;
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if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QCN))
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return -EOPNOTSUPP;
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mailbox_out = mlx4_alloc_cmd_mailbox(priv->mdev->dev);
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if (IS_ERR(mailbox_out))
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return -ENOMEM;
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hw_qcn_stats =
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(struct mlx4_congestion_control_mb_prio_802_1_qau_statistics *)
|
|
mailbox_out->buf;
|
|
|
|
for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
|
|
inmod = priv->port | ((1 << i) << 8) |
|
|
(MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT << 16);
|
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err = mlx4_cmd_box(priv->mdev->dev, mailbox_in_dma,
|
|
mailbox_out->dma, inmod,
|
|
MLX4_CONGESTION_CONTROL_GET_STATISTICS,
|
|
MLX4_CMD_CONGESTION_CTRL_OPCODE,
|
|
MLX4_CMD_TIME_CLASS_C,
|
|
MLX4_CMD_NATIVE);
|
|
if (err) {
|
|
mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
|
|
return err;
|
|
}
|
|
qcn_stats->rppp_rp_centiseconds[i] =
|
|
be64_to_cpu(hw_qcn_stats->rppp_rp_centiseconds);
|
|
qcn_stats->rppp_created_rps[i] =
|
|
be32_to_cpu(hw_qcn_stats->rppp_created_rps);
|
|
}
|
|
mlx4_free_cmd_mailbox(priv->mdev->dev, mailbox_out);
|
|
return 0;
|
|
}
|
|
|
|
const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops = {
|
|
.ieee_getets = mlx4_en_dcbnl_ieee_getets,
|
|
.ieee_setets = mlx4_en_dcbnl_ieee_setets,
|
|
.ieee_getmaxrate = mlx4_en_dcbnl_ieee_getmaxrate,
|
|
.ieee_setmaxrate = mlx4_en_dcbnl_ieee_setmaxrate,
|
|
.ieee_getpfc = mlx4_en_dcbnl_ieee_getpfc,
|
|
.ieee_setpfc = mlx4_en_dcbnl_ieee_setpfc,
|
|
|
|
.getdcbx = mlx4_en_dcbnl_getdcbx,
|
|
.setdcbx = mlx4_en_dcbnl_setdcbx,
|
|
.ieee_getqcn = mlx4_en_dcbnl_ieee_getqcn,
|
|
.ieee_setqcn = mlx4_en_dcbnl_ieee_setqcn,
|
|
.ieee_getqcnstats = mlx4_en_dcbnl_ieee_getqcnstats,
|
|
};
|
|
|
|
const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops = {
|
|
.ieee_getpfc = mlx4_en_dcbnl_ieee_getpfc,
|
|
.ieee_setpfc = mlx4_en_dcbnl_ieee_setpfc,
|
|
|
|
.getdcbx = mlx4_en_dcbnl_getdcbx,
|
|
.setdcbx = mlx4_en_dcbnl_setdcbx,
|
|
};
|