707 lines
18 KiB
C
707 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "clk-stm32-core.h"
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#include "reset-stm32.h"
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static DEFINE_SPINLOCK(rlock);
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static int stm32_rcc_clock_init(struct device *dev,
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const struct of_device_id *match,
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void __iomem *base)
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{
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const struct stm32_rcc_match_data *data = match->data;
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struct clk_hw_onecell_data *clk_data = data->hw_clks;
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struct device_node *np = dev_of_node(dev);
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struct clk_hw **hws;
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int n, max_binding;
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max_binding = data->maxbinding;
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clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->num = max_binding;
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hws = clk_data->hws;
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for (n = 0; n < max_binding; n++)
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hws[n] = ERR_PTR(-ENOENT);
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for (n = 0; n < data->num_clocks; n++) {
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const struct clock_config *cfg_clock = &data->tab_clocks[n];
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struct clk_hw *hw = ERR_PTR(-ENOENT);
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if (data->check_security &&
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data->check_security(base, cfg_clock))
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continue;
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if (cfg_clock->func)
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hw = (*cfg_clock->func)(dev, data, base, &rlock,
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cfg_clock);
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if (IS_ERR(hw)) {
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dev_err(dev, "Can't register clk %d: %ld\n", n,
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PTR_ERR(hw));
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return PTR_ERR(hw);
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}
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if (cfg_clock->id != NO_ID)
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hws[cfg_clock->id] = hw;
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}
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return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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}
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int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
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void __iomem *base)
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{
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const struct of_device_id *match;
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int err;
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match = of_match_node(match_data, dev_of_node(dev));
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if (!match) {
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dev_err(dev, "match data not found\n");
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return -ENODEV;
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}
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/* RCC Reset Configuration */
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err = stm32_rcc_reset_init(dev, match, base);
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if (err) {
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pr_err("stm32 reset failed to initialize\n");
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return err;
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}
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/* RCC Clock Configuration */
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err = stm32_rcc_clock_init(dev, match, base);
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if (err) {
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pr_err("stm32 clock failed to initialize\n");
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return err;
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}
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return 0;
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}
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static u8 stm32_mux_get_parent(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 mux_id)
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{
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const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
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u32 mask = BIT(mux->width) - 1;
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u32 val;
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val = readl(base + mux->offset) >> mux->shift;
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val &= mask;
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return val;
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}
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static int stm32_mux_set_parent(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 mux_id, u8 index)
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{
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const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
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u32 mask = BIT(mux->width) - 1;
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u32 reg = readl(base + mux->offset);
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u32 val = index << mux->shift;
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reg &= ~(mask << mux->shift);
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reg |= val;
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writel(reg, base + mux->offset);
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return 0;
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}
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static void stm32_gate_endisable(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 gate_id, int enable)
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{
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const struct stm32_gate_cfg *gate = &data->gates[gate_id];
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void __iomem *addr = base + gate->offset;
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if (enable) {
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if (data->gate_cpt[gate_id]++ > 0)
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return;
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if (gate->set_clr != 0)
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writel(BIT(gate->bit_idx), addr);
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else
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writel(readl(addr) | BIT(gate->bit_idx), addr);
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} else {
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if (--data->gate_cpt[gate_id] > 0)
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return;
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if (gate->set_clr != 0)
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writel(BIT(gate->bit_idx), addr + gate->set_clr);
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else
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writel(readl(addr) & ~BIT(gate->bit_idx), addr);
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}
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}
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static void stm32_gate_disable_unused(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 gate_id)
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{
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const struct stm32_gate_cfg *gate = &data->gates[gate_id];
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void __iomem *addr = base + gate->offset;
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if (data->gate_cpt[gate_id] > 0)
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return;
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if (gate->set_clr != 0)
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writel(BIT(gate->bit_idx), addr + gate->set_clr);
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else
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writel(readl(addr) & ~BIT(gate->bit_idx), addr);
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}
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static int stm32_gate_is_enabled(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 gate_id)
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{
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const struct stm32_gate_cfg *gate = &data->gates[gate_id];
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return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
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}
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(const struct clk_div_table *table,
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unsigned int val, unsigned long flags, u8 width)
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{
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if (flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (table)
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return _get_table_div(table, val);
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return val + 1;
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}
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static unsigned long stm32_divider_get_rate(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 div_id,
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unsigned long parent_rate)
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{
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const struct stm32_div_cfg *divider = &data->dividers[div_id];
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unsigned int val;
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unsigned int div;
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val = readl(base + divider->offset) >> divider->shift;
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val &= clk_div_mask(divider->width);
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div = _get_div(divider->table, val, divider->flags, divider->width);
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if (!div) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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div_id);
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return parent_rate;
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}
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return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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}
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static int stm32_divider_set_rate(void __iomem *base,
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struct clk_stm32_clock_data *data,
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u16 div_id, unsigned long rate,
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unsigned long parent_rate)
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{
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const struct stm32_div_cfg *divider = &data->dividers[div_id];
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int value;
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u32 val;
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value = divider_get_val(rate, parent_rate, divider->table,
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divider->width, divider->flags);
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if (value < 0)
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return value;
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = clk_div_mask(divider->width) << (divider->shift + 16);
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} else {
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val = readl(base + divider->offset);
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val &= ~(clk_div_mask(divider->width) << divider->shift);
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}
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val |= (u32)value << divider->shift;
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writel(val, base + divider->offset);
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return 0;
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}
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static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
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return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
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}
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static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(mux->lock, flags);
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stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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const struct clk_ops clk_stm32_mux_ops = {
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.determine_rate = __clk_mux_determine_rate,
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.get_parent = clk_stm32_mux_get_parent,
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.set_parent = clk_stm32_mux_set_parent,
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};
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static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
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{
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struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(gate->lock, flags);
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stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int clk_stm32_gate_enable(struct clk_hw *hw)
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{
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clk_stm32_gate_endisable(hw, 1);
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return 0;
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}
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static void clk_stm32_gate_disable(struct clk_hw *hw)
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{
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clk_stm32_gate_endisable(hw, 0);
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}
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static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
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{
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struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
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return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
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}
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static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
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{
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struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(gate->lock, flags);
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stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
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spin_unlock_irqrestore(gate->lock, flags);
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}
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const struct clk_ops clk_stm32_gate_ops = {
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.enable = clk_stm32_gate_enable,
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.disable = clk_stm32_gate_disable,
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.is_enabled = clk_stm32_gate_is_enabled,
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.disable_unused = clk_stm32_gate_disable_unused,
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};
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static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_stm32_div *div = to_clk_stm32_divider(hw);
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unsigned long flags = 0;
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int ret;
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if (div->div_id == NO_STM32_DIV)
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return rate;
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spin_lock_irqsave(div->lock, flags);
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ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
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spin_unlock_irqrestore(div->lock, flags);
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return ret;
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}
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static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_stm32_div *div = to_clk_stm32_divider(hw);
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const struct stm32_div_cfg *divider;
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if (div->div_id == NO_STM32_DIV)
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return rate;
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divider = &div->clock_data->dividers[div->div_id];
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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u32 val;
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val = readl(div->base + divider->offset) >> divider->shift;
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val &= clk_div_mask(divider->width);
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return divider_ro_round_rate(hw, rate, prate, divider->table,
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divider->width, divider->flags,
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val);
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}
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return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
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rate, prate, divider->table,
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divider->width, divider->flags);
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}
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static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_stm32_div *div = to_clk_stm32_divider(hw);
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if (div->div_id == NO_STM32_DIV)
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return parent_rate;
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return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
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}
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const struct clk_ops clk_stm32_divider_ops = {
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.recalc_rate = clk_stm32_divider_recalc_rate,
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.round_rate = clk_stm32_divider_round_rate,
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.set_rate = clk_stm32_divider_set_rate,
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};
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static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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int ret;
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if (composite->div_id == NO_STM32_DIV)
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return rate;
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spin_lock_irqsave(composite->lock, flags);
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ret = stm32_divider_set_rate(composite->base, composite->clock_data,
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composite->div_id, rate, parent_rate);
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spin_unlock_irqrestore(composite->lock, flags);
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return ret;
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}
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static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->div_id == NO_STM32_DIV)
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return parent_rate;
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return stm32_divider_get_rate(composite->base, composite->clock_data,
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composite->div_id, parent_rate);
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}
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static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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const struct stm32_div_cfg *divider;
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unsigned long rate;
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if (composite->div_id == NO_STM32_DIV)
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return 0;
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divider = &composite->clock_data->dividers[composite->div_id];
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/* if read only, just return current value */
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if (divider->flags & CLK_DIVIDER_READ_ONLY) {
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u32 val;
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val = readl(composite->base + divider->offset) >> divider->shift;
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val &= clk_div_mask(divider->width);
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rate = divider_ro_round_rate(hw, req->rate, &req->best_parent_rate,
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divider->table, divider->width, divider->flags,
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val);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
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req->rate, &req->best_parent_rate,
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divider->table, divider->width, divider->flags);
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if (rate < 0)
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return rate;
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req->rate = rate;
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return 0;
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}
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static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
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}
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static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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unsigned long flags = 0;
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spin_lock_irqsave(composite->lock, flags);
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stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
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spin_unlock_irqrestore(composite->lock, flags);
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if (composite->clock_data->is_multi_mux) {
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struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
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if (other_mux_hw) {
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struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
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clk_hw_reparent(other_mux_hw, hwp);
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}
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}
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return 0;
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}
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static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
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{
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struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
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if (composite->gate_id == NO_STM32_GATE)
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return (__clk_get_enable_count(hw->clk) > 0);
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return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
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}
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|
|
|
#define MUX_SAFE_POSITION 0
|
|
|
|
static int clk_stm32_has_safe_mux(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
|
|
|
|
return !!(mux->flags & MUX_SAFE);
|
|
}
|
|
|
|
static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
|
|
if (!clk_stm32_composite_is_enabled(hw)) {
|
|
unsigned long flags = 0;
|
|
|
|
if (composite->clock_data->is_multi_mux) {
|
|
struct clk_hw *other_mux_hw = NULL;
|
|
|
|
other_mux_hw = composite->clock_data->is_multi_mux(hw);
|
|
|
|
if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
|
|
return;
|
|
}
|
|
|
|
spin_lock_irqsave(composite->lock, flags);
|
|
|
|
stm32_mux_set_parent(composite->base, composite->clock_data,
|
|
composite->mux_id, MUX_SAFE_POSITION);
|
|
|
|
spin_unlock_irqrestore(composite->lock, flags);
|
|
}
|
|
}
|
|
|
|
static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
int sel = clk_hw_get_parent_index(hw);
|
|
unsigned long flags = 0;
|
|
|
|
spin_lock_irqsave(composite->lock, flags);
|
|
|
|
stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
|
|
|
|
spin_unlock_irqrestore(composite->lock, flags);
|
|
}
|
|
|
|
static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
unsigned long flags = 0;
|
|
|
|
spin_lock_irqsave(composite->lock, flags);
|
|
|
|
stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
|
|
|
|
spin_unlock_irqrestore(composite->lock, flags);
|
|
}
|
|
|
|
static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
|
|
if (composite->gate_id == NO_STM32_GATE)
|
|
return 0;
|
|
|
|
clk_stm32_composite_gate_endisable(hw, 1);
|
|
|
|
if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
|
|
clk_stm32_safe_restore_position_mux(hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
|
|
if (composite->gate_id == NO_STM32_GATE)
|
|
return;
|
|
|
|
clk_stm32_composite_gate_endisable(hw, 0);
|
|
|
|
if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
|
|
clk_stm32_set_safe_position_mux(hw);
|
|
}
|
|
|
|
static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
|
|
{
|
|
struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
|
|
unsigned long flags = 0;
|
|
|
|
if (composite->gate_id == NO_STM32_GATE)
|
|
return;
|
|
|
|
spin_lock_irqsave(composite->lock, flags);
|
|
|
|
stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
|
|
|
|
spin_unlock_irqrestore(composite->lock, flags);
|
|
}
|
|
|
|
const struct clk_ops clk_stm32_composite_ops = {
|
|
.set_rate = clk_stm32_composite_set_rate,
|
|
.recalc_rate = clk_stm32_composite_recalc_rate,
|
|
.determine_rate = clk_stm32_composite_determine_rate,
|
|
.get_parent = clk_stm32_composite_get_parent,
|
|
.set_parent = clk_stm32_composite_set_parent,
|
|
.enable = clk_stm32_composite_gate_enable,
|
|
.disable = clk_stm32_composite_gate_disable,
|
|
.is_enabled = clk_stm32_composite_is_enabled,
|
|
.disable_unused = clk_stm32_composite_disable_unused,
|
|
};
|
|
|
|
struct clk_hw *clk_stm32_mux_register(struct device *dev,
|
|
const struct stm32_rcc_match_data *data,
|
|
void __iomem *base,
|
|
spinlock_t *lock,
|
|
const struct clock_config *cfg)
|
|
{
|
|
struct clk_stm32_mux *mux = cfg->clock_cfg;
|
|
struct clk_hw *hw = &mux->hw;
|
|
int err;
|
|
|
|
mux->base = base;
|
|
mux->lock = lock;
|
|
mux->clock_data = data->clock_data;
|
|
|
|
err = clk_hw_register(dev, hw);
|
|
if (err)
|
|
return ERR_PTR(err);
|
|
|
|
return hw;
|
|
}
|
|
|
|
struct clk_hw *clk_stm32_gate_register(struct device *dev,
|
|
const struct stm32_rcc_match_data *data,
|
|
void __iomem *base,
|
|
spinlock_t *lock,
|
|
const struct clock_config *cfg)
|
|
{
|
|
struct clk_stm32_gate *gate = cfg->clock_cfg;
|
|
struct clk_hw *hw = &gate->hw;
|
|
int err;
|
|
|
|
gate->base = base;
|
|
gate->lock = lock;
|
|
gate->clock_data = data->clock_data;
|
|
|
|
err = clk_hw_register(dev, hw);
|
|
if (err)
|
|
return ERR_PTR(err);
|
|
|
|
return hw;
|
|
}
|
|
|
|
struct clk_hw *clk_stm32_div_register(struct device *dev,
|
|
const struct stm32_rcc_match_data *data,
|
|
void __iomem *base,
|
|
spinlock_t *lock,
|
|
const struct clock_config *cfg)
|
|
{
|
|
struct clk_stm32_div *div = cfg->clock_cfg;
|
|
struct clk_hw *hw = &div->hw;
|
|
int err;
|
|
|
|
div->base = base;
|
|
div->lock = lock;
|
|
div->clock_data = data->clock_data;
|
|
|
|
err = clk_hw_register(dev, hw);
|
|
if (err)
|
|
return ERR_PTR(err);
|
|
|
|
return hw;
|
|
}
|
|
|
|
struct clk_hw *clk_stm32_composite_register(struct device *dev,
|
|
const struct stm32_rcc_match_data *data,
|
|
void __iomem *base,
|
|
spinlock_t *lock,
|
|
const struct clock_config *cfg)
|
|
{
|
|
struct clk_stm32_composite *composite = cfg->clock_cfg;
|
|
struct clk_hw *hw = &composite->hw;
|
|
int err;
|
|
|
|
composite->base = base;
|
|
composite->lock = lock;
|
|
composite->clock_data = data->clock_data;
|
|
|
|
err = clk_hw_register(dev, hw);
|
|
if (err)
|
|
return ERR_PTR(err);
|
|
|
|
return hw;
|
|
}
|