354 lines
8.6 KiB
C
354 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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* Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
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*/
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/*
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* clock and PLL management functions
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*/
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#include <linux/kernel.h>
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#include <linux/via-core.h>
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#include "via_clock.h"
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#include "global.h"
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#include "debug.h"
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static const char *via_slap = "Please slap VIA Technologies to motivate them "
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"releasing full documentation for your platform!\n";
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static inline u32 cle266_encode_pll(struct via_pll_config pll)
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{
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return (pll.multiplier << 8)
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| (pll.rshift << 6)
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| pll.divisor;
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}
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static inline u32 k800_encode_pll(struct via_pll_config pll)
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{
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return ((pll.divisor - 2) << 16)
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| (pll.rshift << 10)
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| (pll.multiplier - 2);
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}
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static inline u32 vx855_encode_pll(struct via_pll_config pll)
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{
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return (pll.divisor << 16)
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| (pll.rshift << 10)
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| pll.multiplier;
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}
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static inline void cle266_set_primary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
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via_write_reg(VIASR, 0x46, data & 0xFF);
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via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
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}
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static inline void k800_set_primary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
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via_write_reg(VIASR, 0x44, data & 0xFF);
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via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
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via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
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}
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static inline void cle266_set_secondary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
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via_write_reg(VIASR, 0x44, data & 0xFF);
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via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
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}
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static inline void k800_set_secondary_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
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via_write_reg(VIASR, 0x4A, data & 0xFF);
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via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
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via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
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}
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static inline void set_engine_pll_encoded(u32 data)
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{
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via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
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via_write_reg(VIASR, 0x47, data & 0xFF);
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via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
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via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
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via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
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}
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static void cle266_set_primary_pll(struct via_pll_config config)
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{
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cle266_set_primary_pll_encoded(cle266_encode_pll(config));
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}
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static void k800_set_primary_pll(struct via_pll_config config)
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{
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k800_set_primary_pll_encoded(k800_encode_pll(config));
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}
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static void vx855_set_primary_pll(struct via_pll_config config)
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{
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k800_set_primary_pll_encoded(vx855_encode_pll(config));
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}
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static void cle266_set_secondary_pll(struct via_pll_config config)
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{
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cle266_set_secondary_pll_encoded(cle266_encode_pll(config));
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}
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static void k800_set_secondary_pll(struct via_pll_config config)
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{
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k800_set_secondary_pll_encoded(k800_encode_pll(config));
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}
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static void vx855_set_secondary_pll(struct via_pll_config config)
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{
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k800_set_secondary_pll_encoded(vx855_encode_pll(config));
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}
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static void k800_set_engine_pll(struct via_pll_config config)
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{
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set_engine_pll_encoded(k800_encode_pll(config));
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}
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static void vx855_set_engine_pll(struct via_pll_config config)
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{
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set_engine_pll_encoded(vx855_encode_pll(config));
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}
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static void set_primary_pll_state(u8 state)
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{
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u8 value;
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switch (state) {
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case VIA_STATE_ON:
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value = 0x20;
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break;
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case VIA_STATE_OFF:
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value = 0x00;
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break;
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default:
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return;
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}
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via_write_reg_mask(VIASR, 0x2D, value, 0x30);
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}
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static void set_secondary_pll_state(u8 state)
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{
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u8 value;
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switch (state) {
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case VIA_STATE_ON:
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value = 0x08;
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break;
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case VIA_STATE_OFF:
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value = 0x00;
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break;
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default:
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return;
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}
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via_write_reg_mask(VIASR, 0x2D, value, 0x0C);
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}
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static void set_engine_pll_state(u8 state)
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{
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u8 value;
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switch (state) {
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case VIA_STATE_ON:
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value = 0x02;
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break;
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case VIA_STATE_OFF:
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value = 0x00;
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break;
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default:
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return;
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}
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via_write_reg_mask(VIASR, 0x2D, value, 0x03);
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}
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static void set_primary_clock_state(u8 state)
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{
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u8 value;
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switch (state) {
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case VIA_STATE_ON:
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value = 0x20;
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break;
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case VIA_STATE_OFF:
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value = 0x00;
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break;
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default:
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return;
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}
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via_write_reg_mask(VIASR, 0x1B, value, 0x30);
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}
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static void set_secondary_clock_state(u8 state)
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{
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u8 value;
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switch (state) {
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case VIA_STATE_ON:
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value = 0x80;
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break;
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case VIA_STATE_OFF:
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value = 0x00;
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break;
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default:
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return;
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}
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via_write_reg_mask(VIASR, 0x1B, value, 0xC0);
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}
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static inline u8 set_clock_source_common(enum via_clksrc source, bool use_pll)
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{
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u8 data = 0;
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switch (source) {
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case VIA_CLKSRC_X1:
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data = 0x00;
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break;
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case VIA_CLKSRC_TVX1:
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data = 0x02;
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break;
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case VIA_CLKSRC_TVPLL:
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data = 0x04; /* 0x06 should be the same */
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break;
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case VIA_CLKSRC_DVP1TVCLKR:
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data = 0x0A;
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break;
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case VIA_CLKSRC_CAP0:
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data = 0xC;
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break;
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case VIA_CLKSRC_CAP1:
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data = 0x0E;
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break;
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}
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if (!use_pll)
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data |= 1;
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return data;
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}
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static void set_primary_clock_source(enum via_clksrc source, bool use_pll)
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{
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u8 data = set_clock_source_common(source, use_pll) << 4;
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via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
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}
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static void set_secondary_clock_source(enum via_clksrc source, bool use_pll)
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{
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u8 data = set_clock_source_common(source, use_pll);
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via_write_reg_mask(VIACR, 0x6C, data, 0x0F);
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}
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static void dummy_set_clock_state(u8 state)
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{
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printk(KERN_INFO "Using undocumented set clock state.\n%s", via_slap);
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}
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static void dummy_set_clock_source(enum via_clksrc source, bool use_pll)
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{
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printk(KERN_INFO "Using undocumented set clock source.\n%s", via_slap);
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}
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static void dummy_set_pll_state(u8 state)
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{
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printk(KERN_INFO "Using undocumented set PLL state.\n%s", via_slap);
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}
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static void dummy_set_pll(struct via_pll_config config)
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{
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printk(KERN_INFO "Using undocumented set PLL.\n%s", via_slap);
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}
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static void noop_set_clock_state(u8 state)
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{
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}
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void via_clock_init(struct via_clock *clock, int gfx_chip)
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{
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switch (gfx_chip) {
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case UNICHROME_CLE266:
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case UNICHROME_K400:
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clock->set_primary_clock_state = dummy_set_clock_state;
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clock->set_primary_clock_source = dummy_set_clock_source;
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clock->set_primary_pll_state = dummy_set_pll_state;
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clock->set_primary_pll = cle266_set_primary_pll;
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clock->set_secondary_clock_state = dummy_set_clock_state;
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clock->set_secondary_clock_source = dummy_set_clock_source;
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clock->set_secondary_pll_state = dummy_set_pll_state;
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clock->set_secondary_pll = cle266_set_secondary_pll;
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clock->set_engine_pll_state = dummy_set_pll_state;
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clock->set_engine_pll = dummy_set_pll;
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break;
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case UNICHROME_K800:
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case UNICHROME_PM800:
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case UNICHROME_CN700:
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case UNICHROME_CX700:
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case UNICHROME_CN750:
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case UNICHROME_K8M890:
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case UNICHROME_P4M890:
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case UNICHROME_P4M900:
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case UNICHROME_VX800:
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clock->set_primary_clock_state = set_primary_clock_state;
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clock->set_primary_clock_source = set_primary_clock_source;
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clock->set_primary_pll_state = set_primary_pll_state;
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clock->set_primary_pll = k800_set_primary_pll;
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clock->set_secondary_clock_state = set_secondary_clock_state;
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clock->set_secondary_clock_source = set_secondary_clock_source;
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clock->set_secondary_pll_state = set_secondary_pll_state;
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clock->set_secondary_pll = k800_set_secondary_pll;
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clock->set_engine_pll_state = set_engine_pll_state;
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clock->set_engine_pll = k800_set_engine_pll;
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break;
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case UNICHROME_VX855:
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case UNICHROME_VX900:
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clock->set_primary_clock_state = set_primary_clock_state;
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clock->set_primary_clock_source = set_primary_clock_source;
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clock->set_primary_pll_state = set_primary_pll_state;
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clock->set_primary_pll = vx855_set_primary_pll;
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clock->set_secondary_clock_state = set_secondary_clock_state;
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clock->set_secondary_clock_source = set_secondary_clock_source;
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clock->set_secondary_pll_state = set_secondary_pll_state;
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clock->set_secondary_pll = vx855_set_secondary_pll;
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clock->set_engine_pll_state = set_engine_pll_state;
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clock->set_engine_pll = vx855_set_engine_pll;
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break;
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}
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if (machine_is_olpc()) {
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/* The OLPC XO-1.5 cannot suspend/resume reliably if the
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* IGA1/IGA2 clocks are set as on or off (memory rot
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* occasionally happens during suspend under such
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* configurations).
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*
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* The only known stable scenario is to leave this bits as-is,
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* which in their default states are documented to enable the
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* clock only when it is needed.
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*/
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clock->set_primary_clock_state = noop_set_clock_state;
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clock->set_secondary_clock_state = noop_set_clock_state;
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}
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}
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