332 lines
9.5 KiB
C
332 lines
9.5 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __CI_DPM_H__
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#define __CI_DPM_H__
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#include "ppsmc.h"
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 6
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#define SMU__NUM_LCLK_DPM_LEVELS 8
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#include "smu7_discrete.h"
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#define CISLANDS_MAX_HARDWARE_POWERLEVELS 2
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struct ci_pl {
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u32 mclk;
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u32 sclk;
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enum radeon_pcie_gen pcie_gen;
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u16 pcie_lane;
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};
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struct ci_ps {
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u16 performance_level_count;
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bool dc_compatible;
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u32 sclk_t;
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struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];
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};
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struct ci_dpm_level {
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bool enabled;
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u32 value;
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u32 param1;
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};
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#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define MAX_REGULAR_DPM_NUMBER 8
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#define CISLAND_MINIMUM_ENGINE_CLOCK 800
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struct ci_single_dpm_table {
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u32 count;
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struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
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};
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struct ci_dpm_table {
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struct ci_single_dpm_table sclk_table;
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struct ci_single_dpm_table mclk_table;
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struct ci_single_dpm_table pcie_speed_table;
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struct ci_single_dpm_table vddc_table;
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struct ci_single_dpm_table vddci_table;
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struct ci_single_dpm_table mvdd_table;
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};
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struct ci_mc_reg_entry {
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u32 mclk_max;
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u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_mc_reg_table {
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u8 last;
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u8 num_entries;
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u16 valid_flag;
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struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
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SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
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};
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struct ci_ulv_parm
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{
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bool supported;
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u32 cg_ulv_parameter;
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u32 volt_change_delay;
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struct ci_pl pl;
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};
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#define CISLANDS_MAX_LEAKAGE_COUNT 8
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struct ci_leakage_voltage {
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u16 count;
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u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];
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u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];
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};
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struct ci_dpm_level_enable_mask {
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u32 uvd_dpm_enable_mask;
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u32 vce_dpm_enable_mask;
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u32 acp_dpm_enable_mask;
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u32 samu_dpm_enable_mask;
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u32 sclk_dpm_enable_mask;
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u32 mclk_dpm_enable_mask;
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u32 pcie_dpm_enable_mask;
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};
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struct ci_vbios_boot_state
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{
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u16 mvdd_bootup_value;
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u16 vddc_bootup_value;
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u16 vddci_bootup_value;
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u32 sclk_bootup_value;
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u32 mclk_bootup_value;
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u16 pcie_gen_bootup_value;
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u16 pcie_lane_bootup_value;
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};
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struct ci_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_func_cntl_4;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 dll_cntl;
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u32 mclk_pwrmgt_cntl;
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u32 mpll_ad_func_cntl;
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u32 mpll_dq_func_cntl;
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u32 mpll_func_cntl;
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u32 mpll_func_cntl_1;
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u32 mpll_func_cntl_2;
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u32 mpll_ss1;
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u32 mpll_ss2;
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};
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struct ci_thermal_temperature_setting {
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s32 temperature_low;
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s32 temperature_high;
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s32 temperature_shutdown;
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};
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struct ci_pcie_perf_range {
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u16 max;
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u16 min;
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};
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enum ci_pt_config_reg_type {
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CISLANDS_CONFIGREG_MMR = 0,
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CISLANDS_CONFIGREG_SMC_IND,
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CISLANDS_CONFIGREG_DIDT_IND,
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CISLANDS_CONFIGREG_CACHE,
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CISLANDS_CONFIGREG_MAX
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};
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#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
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#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
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#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
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struct ci_pt_config_reg {
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u32 offset;
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u32 mask;
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u32 shift;
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u32 value;
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enum ci_pt_config_reg_type type;
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};
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struct ci_pt_defaults {
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u8 svi_load_line_en;
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u8 svi_load_line_vddc;
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u8 tdc_vddc_throttle_release_limit_perc;
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u8 tdc_mawt;
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u8 tdc_waterfall_ctl;
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u8 dte_ambient_temp_base;
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u32 display_cac;
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u32 bapm_temp_gradient;
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u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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struct ci_power_info {
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struct ci_dpm_table dpm_table;
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u32 voltage_control;
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u32 mvdd_control;
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u32 vddci_control;
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u32 active_auto_throttle_sources;
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struct ci_clock_registers clock_registers;
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u16 acpi_vddc;
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u16 acpi_vddci;
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enum radeon_pcie_gen force_pcie_gen;
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enum radeon_pcie_gen acpi_pcie_gen;
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struct ci_leakage_voltage vddc_leakage;
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struct ci_leakage_voltage vddci_leakage;
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u16 max_vddc_in_pp_table;
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u16 min_vddc_in_pp_table;
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u16 max_vddci_in_pp_table;
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u16 min_vddci_in_pp_table;
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u32 mclk_strobe_mode_threshold;
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u32 mclk_stutter_mode_threshold;
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u32 mclk_edc_enable_threshold;
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u32 mclk_edc_wr_enable_threshold;
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struct ci_vbios_boot_state vbios_boot_state;
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/* smc offsets */
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u32 sram_end;
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u32 dpm_table_start;
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u32 soft_regs_start;
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u32 mc_reg_table_start;
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u32 fan_table_start;
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u32 arb_table_start;
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/* smc tables */
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SMU7_Discrete_DpmTable smc_state_table;
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SMU7_Discrete_MCRegisters smc_mc_reg_table;
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SMU7_Discrete_PmFuses smc_powertune_table;
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/* other stuff */
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struct ci_mc_reg_table mc_reg_table;
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struct atom_voltage_table vddc_voltage_table;
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struct atom_voltage_table vddci_voltage_table;
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struct atom_voltage_table mvdd_voltage_table;
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struct ci_ulv_parm ulv;
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u32 power_containment_features;
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const struct ci_pt_defaults *powertune_defaults;
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u32 dte_tj_offset;
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bool vddc_phase_shed_control;
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struct ci_thermal_temperature_setting thermal_temp_setting;
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struct ci_dpm_level_enable_mask dpm_level_enable_mask;
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u32 need_update_smu7_dpm_table;
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u32 sclk_dpm_key_disabled;
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u32 mclk_dpm_key_disabled;
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u32 pcie_dpm_key_disabled;
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struct ci_pcie_perf_range pcie_gen_performance;
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struct ci_pcie_perf_range pcie_lane_performance;
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struct ci_pcie_perf_range pcie_gen_powersaving;
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struct ci_pcie_perf_range pcie_lane_powersaving;
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u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];
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u32 mclk_activity_target;
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u32 low_sclk_interrupt_t;
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u32 last_mclk_dpm_enable_mask;
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u32 sys_pcie_mask;
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/* caps */
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bool caps_power_containment;
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bool caps_cac;
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bool caps_sq_ramping;
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bool caps_db_ramping;
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bool caps_td_ramping;
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bool caps_tcp_ramping;
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bool caps_fps;
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bool caps_sclk_ds;
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bool caps_sclk_ss_support;
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bool caps_mclk_ss_support;
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bool caps_uvd_dpm;
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bool caps_vce_dpm;
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bool caps_samu_dpm;
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bool caps_acp_dpm;
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bool caps_automatic_dc_transition;
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bool caps_sclk_throttle_low_notification;
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bool caps_dynamic_ac_timing;
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/* flags */
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bool thermal_protection;
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bool pcie_performance_request;
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bool dynamic_ss;
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bool dll_default_on;
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bool cac_enabled;
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bool uvd_enabled;
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bool battery_state;
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bool pspp_notify_required;
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bool mem_gddr5;
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bool enable_bapm_feature;
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bool enable_tdc_limit_feature;
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bool enable_pkg_pwr_tracking_feature;
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bool use_pcie_performance_levels;
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bool use_pcie_powersaving_levels;
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/* driver states */
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struct radeon_ps current_rps;
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struct ci_ps current_ps;
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struct radeon_ps requested_rps;
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struct ci_ps requested_ps;
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};
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#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0
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#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1
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#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2
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#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256
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#define CISLANDS_VRC_DFLT0 0x3FFFC000
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#define CISLANDS_VRC_DFLT1 0x000400
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#define CISLANDS_VRC_DFLT2 0xC00080
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#define CISLANDS_VRC_DFLT3 0xC00200
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#define CISLANDS_VRC_DFLT4 0xC01680
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#define CISLANDS_VRC_DFLT5 0xC00033
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#define CISLANDS_VRC_DFLT6 0xC00033
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#define CISLANDS_VRC_DFLT7 0x3FFFC000
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#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035
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#define CISLAND_TARGETACTIVITY_DFLT 30
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#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10
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#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
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#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
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#define PCIE_PERF_REQ_PECI_GEN1 2
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#define PCIE_PERF_REQ_PECI_GEN2 3
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#define PCIE_PERF_REQ_PECI_GEN3 4
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int ci_copy_bytes_to_smc(struct radeon_device *rdev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit);
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void ci_start_smc(struct radeon_device *rdev);
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void ci_reset_smc(struct radeon_device *rdev);
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int ci_program_jump_on_start(struct radeon_device *rdev);
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void ci_stop_smc_clock(struct radeon_device *rdev);
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void ci_start_smc_clock(struct radeon_device *rdev);
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bool ci_is_smc_running(struct radeon_device *rdev);
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PPSMC_Result ci_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg);
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PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);
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int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);
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int ci_read_smc_sram_dword(struct radeon_device *rdev,
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u32 smc_address, u32 *value, u32 limit);
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int ci_write_smc_sram_dword(struct radeon_device *rdev,
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u32 smc_address, u32 value, u32 limit);
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#endif
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