402 lines
12 KiB
C
402 lines
12 KiB
C
/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "dvo.h"
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#define CH7017_TV_DISPLAY_MODE 0x00
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#define CH7017_FLICKER_FILTER 0x01
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#define CH7017_VIDEO_BANDWIDTH 0x02
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#define CH7017_TEXT_ENHANCEMENT 0x03
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#define CH7017_START_ACTIVE_VIDEO 0x04
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#define CH7017_HORIZONTAL_POSITION 0x05
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#define CH7017_VERTICAL_POSITION 0x06
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#define CH7017_BLACK_LEVEL 0x07
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#define CH7017_CONTRAST_ENHANCEMENT 0x08
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#define CH7017_TV_PLL 0x09
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#define CH7017_TV_PLL_M 0x0a
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#define CH7017_TV_PLL_N 0x0b
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#define CH7017_SUB_CARRIER_0 0x0c
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#define CH7017_CIV_CONTROL 0x10
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#define CH7017_CIV_0 0x11
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#define CH7017_CHROMA_BOOST 0x14
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#define CH7017_CLOCK_MODE 0x1c
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#define CH7017_INPUT_CLOCK 0x1d
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#define CH7017_GPIO_CONTROL 0x1e
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#define CH7017_INPUT_DATA_FORMAT 0x1f
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#define CH7017_CONNECTION_DETECT 0x20
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#define CH7017_DAC_CONTROL 0x21
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#define CH7017_BUFFERED_CLOCK_OUTPUT 0x22
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#define CH7017_DEFEAT_VSYNC 0x47
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#define CH7017_TEST_PATTERN 0x48
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#define CH7017_POWER_MANAGEMENT 0x49
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/** Enables the TV output path. */
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#define CH7017_TV_EN (1 << 0)
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#define CH7017_DAC0_POWER_DOWN (1 << 1)
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#define CH7017_DAC1_POWER_DOWN (1 << 2)
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#define CH7017_DAC2_POWER_DOWN (1 << 3)
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#define CH7017_DAC3_POWER_DOWN (1 << 4)
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/** Powers down the TV out block, and DAC0-3 */
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#define CH7017_TV_POWER_DOWN_EN (1 << 5)
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#define CH7017_VERSION_ID 0x4a
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#define CH7017_DEVICE_ID 0x4b
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#define CH7017_DEVICE_ID_VALUE 0x1b
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#define CH7018_DEVICE_ID_VALUE 0x1a
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#define CH7019_DEVICE_ID_VALUE 0x19
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#define CH7017_XCLK_D2_ADJUST 0x53
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#define CH7017_UP_SCALER_COEFF_0 0x55
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#define CH7017_UP_SCALER_COEFF_1 0x56
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#define CH7017_UP_SCALER_COEFF_2 0x57
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#define CH7017_UP_SCALER_COEFF_3 0x58
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#define CH7017_UP_SCALER_COEFF_4 0x59
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#define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a
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#define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b
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#define CH7017_GPIO_INVERT 0x5c
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#define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d
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#define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e
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#define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f
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/**< Low bits of horizontal active pixel input */
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#define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60
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/** High bits of horizontal active pixel input */
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#define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0)
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/** High bits of vertical active line output */
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#define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3)
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#define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61
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/**< Low bits of vertical active line output */
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#define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62
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/**< Low bits of horizontal active pixel output */
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#define CH7017_LVDS_POWER_DOWN 0x63
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/** High bits of horizontal active pixel output */
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#define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0)
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/** Enables the LVDS power down state transition */
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#define CH7017_LVDS_POWER_DOWN_EN (1 << 6)
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/** Enables the LVDS upscaler */
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#define CH7017_LVDS_UPSCALER_EN (1 << 7)
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#define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
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#define CH7017_LVDS_ENCODING 0x64
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#define CH7017_LVDS_DITHER_2D (1 << 2)
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#define CH7017_LVDS_DITHER_DIS (1 << 3)
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#define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4)
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#define CH7017_LVDS_24_BIT (1 << 5)
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#define CH7017_LVDS_ENCODING_2 0x65
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#define CH7017_LVDS_PLL_CONTROL 0x66
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/** Enables the LVDS panel output path */
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#define CH7017_LVDS_PANEN (1 << 0)
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/** Enables the LVDS panel backlight */
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#define CH7017_LVDS_BKLEN (1 << 3)
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#define CH7017_POWER_SEQUENCING_T1 0x67
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#define CH7017_POWER_SEQUENCING_T2 0x68
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#define CH7017_POWER_SEQUENCING_T3 0x69
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#define CH7017_POWER_SEQUENCING_T4 0x6a
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#define CH7017_POWER_SEQUENCING_T5 0x6b
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#define CH7017_GPIO_DRIVER_TYPE 0x6c
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#define CH7017_GPIO_DATA 0x6d
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#define CH7017_GPIO_DIRECTION_CONTROL 0x6e
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#define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71
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# define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4
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# define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0
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# define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80
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#define CH7017_LVDS_PLL_VCO_CONTROL 0x72
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# define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80
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# define CH7017_LVDS_PLL_VCO_SHIFT 4
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# define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0
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#define CH7017_OUTPUTS_ENABLE 0x73
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# define CH7017_CHARGE_PUMP_LOW 0x0
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# define CH7017_CHARGE_PUMP_HIGH 0x3
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# define CH7017_LVDS_CHANNEL_A (1 << 3)
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# define CH7017_LVDS_CHANNEL_B (1 << 4)
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# define CH7017_TV_DAC_A (1 << 5)
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# define CH7017_TV_DAC_B (1 << 6)
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# define CH7017_DDC_SELECT_DC2 (1 << 7)
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#define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74
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#define CH7017_LVDS_PLL_EMI_REDUCTION 0x75
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#define CH7017_LVDS_POWER_DOWN_FLICKER 0x76
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#define CH7017_LVDS_CONTROL_2 0x78
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# define CH7017_LOOP_FILTER_SHIFT 5
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# define CH7017_PHASE_DETECTOR_SHIFT 0
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#define CH7017_BANG_LIMIT_CONTROL 0x7f
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struct ch7017_priv {
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uint8_t dummy;
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};
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static void ch7017_dump_regs(struct intel_dvo_device *dvo);
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static void ch7017_dpms(struct intel_dvo_device *dvo, int mode);
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static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
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{
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struct i2c_msg msgs[] = {
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{
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 1,
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.buf = &addr,
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},
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = val,
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}
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};
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return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2;
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}
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static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
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{
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uint8_t buf[2] = { addr, val };
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struct i2c_msg msg = {
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 2,
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.buf = buf,
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};
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return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
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}
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/** Probes for a CH7017 on the given bus and slave address. */
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static bool ch7017_init(struct intel_dvo_device *dvo,
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struct i2c_adapter *adapter)
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{
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struct ch7017_priv *priv;
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const char *str;
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u8 val;
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priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL);
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if (priv == NULL)
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return false;
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dvo->i2c_bus = adapter;
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dvo->dev_priv = priv;
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if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val))
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goto fail;
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switch (val) {
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case CH7017_DEVICE_ID_VALUE:
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str = "ch7017";
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break;
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case CH7018_DEVICE_ID_VALUE:
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str = "ch7018";
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break;
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case CH7019_DEVICE_ID_VALUE:
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str = "ch7019";
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break;
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default:
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DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
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"slave %d.\n",
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val, adapter->name,dvo->slave_addr);
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goto fail;
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}
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DRM_DEBUG_KMS("%s detected on %s, addr %d\n",
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str, adapter->name, dvo->slave_addr);
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return true;
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fail:
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kfree(priv);
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return false;
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}
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static enum drm_connector_status ch7017_detect(struct intel_dvo_device *dvo)
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{
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return connector_status_connected;
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}
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static enum drm_mode_status ch7017_mode_valid(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode)
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{
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if (mode->clock > 160000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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static void ch7017_mode_set(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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uint8_t lvds_pll_feedback_div, lvds_pll_vco_control;
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uint8_t outputs_enable, lvds_control_2, lvds_power_down;
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uint8_t horizontal_active_pixel_input;
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uint8_t horizontal_active_pixel_output, vertical_active_line_output;
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uint8_t active_input_line_output;
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DRM_DEBUG_KMS("Registers before mode setting\n");
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ch7017_dump_regs(dvo);
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/* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
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if (mode->clock < 100000) {
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outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW;
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lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
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(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
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(13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
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lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
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(2 << CH7017_LVDS_PLL_VCO_SHIFT) |
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(3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
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lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) |
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(0 << CH7017_PHASE_DETECTOR_SHIFT);
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} else {
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outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH;
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lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
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(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
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(3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
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lvds_pll_feedback_div = 35;
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lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) |
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(0 << CH7017_PHASE_DETECTOR_SHIFT);
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if (1) { /* XXX: dual channel panel detection. Assume yes for now. */
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outputs_enable |= CH7017_LVDS_CHANNEL_B;
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lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
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(2 << CH7017_LVDS_PLL_VCO_SHIFT) |
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(13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
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} else {
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lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
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(1 << CH7017_LVDS_PLL_VCO_SHIFT) |
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(13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
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}
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}
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horizontal_active_pixel_input = mode->hdisplay & 0x00ff;
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vertical_active_line_output = mode->vdisplay & 0x00ff;
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horizontal_active_pixel_output = mode->hdisplay & 0x00ff;
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active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) |
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(((mode->vdisplay & 0x0700) >> 8) << 3);
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lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED |
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(mode->hdisplay & 0x0700) >> 8;
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ch7017_dpms(dvo, DRM_MODE_DPMS_OFF);
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ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT,
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horizontal_active_pixel_input);
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ch7017_write(dvo, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT,
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horizontal_active_pixel_output);
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ch7017_write(dvo, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT,
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vertical_active_line_output);
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ch7017_write(dvo, CH7017_ACTIVE_INPUT_LINE_OUTPUT,
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active_input_line_output);
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ch7017_write(dvo, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control);
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ch7017_write(dvo, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div);
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ch7017_write(dvo, CH7017_LVDS_CONTROL_2, lvds_control_2);
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ch7017_write(dvo, CH7017_OUTPUTS_ENABLE, outputs_enable);
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/* Turn the LVDS back on with new settings. */
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ch7017_write(dvo, CH7017_LVDS_POWER_DOWN, lvds_power_down);
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DRM_DEBUG_KMS("Registers after mode setting\n");
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ch7017_dump_regs(dvo);
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}
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/* set the CH7017 power state */
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static void ch7017_dpms(struct intel_dvo_device *dvo, int mode)
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{
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uint8_t val;
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ch7017_read(dvo, CH7017_LVDS_POWER_DOWN, &val);
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/* Turn off TV/VGA, and never turn it on since we don't support it. */
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ch7017_write(dvo, CH7017_POWER_MANAGEMENT,
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CH7017_DAC0_POWER_DOWN |
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CH7017_DAC1_POWER_DOWN |
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CH7017_DAC2_POWER_DOWN |
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CH7017_DAC3_POWER_DOWN |
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CH7017_TV_POWER_DOWN_EN);
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if (mode == DRM_MODE_DPMS_ON) {
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/* Turn on the LVDS */
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ch7017_write(dvo, CH7017_LVDS_POWER_DOWN,
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val & ~CH7017_LVDS_POWER_DOWN_EN);
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} else {
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/* Turn off the LVDS */
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ch7017_write(dvo, CH7017_LVDS_POWER_DOWN,
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val | CH7017_LVDS_POWER_DOWN_EN);
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}
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/* XXX: Should actually wait for update power status somehow */
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msleep(20);
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}
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static void ch7017_dump_regs(struct intel_dvo_device *dvo)
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{
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uint8_t val;
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#define DUMP(reg) \
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do { \
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ch7017_read(dvo, reg, &val); \
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DRM_DEBUG_KMS(#reg ": %02x\n", val); \
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} while (0)
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DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
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DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT);
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DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT);
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DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT);
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DUMP(CH7017_LVDS_PLL_VCO_CONTROL);
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DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV);
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DUMP(CH7017_LVDS_CONTROL_2);
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DUMP(CH7017_OUTPUTS_ENABLE);
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DUMP(CH7017_LVDS_POWER_DOWN);
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}
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static void ch7017_destroy(struct intel_dvo_device *dvo)
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{
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struct ch7017_priv *priv = dvo->dev_priv;
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if (priv) {
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kfree(priv);
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dvo->dev_priv = NULL;
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}
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}
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struct intel_dvo_dev_ops ch7017_ops = {
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.init = ch7017_init,
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.detect = ch7017_detect,
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.mode_valid = ch7017_mode_valid,
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.mode_set = ch7017_mode_set,
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.dpms = ch7017_dpms,
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.dump_regs = ch7017_dump_regs,
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.destroy = ch7017_destroy,
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};
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