756 lines
19 KiB
C
756 lines
19 KiB
C
/*
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* include/asm-i386/processor.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*/
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#ifndef __ASM_I386_PROCESSOR_H
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#define __ASM_I386_PROCESSOR_H
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#include <asm/vm86.h>
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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#include <asm/system.h>
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <asm/percpu.h>
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <asm/processor-flags.h>
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/* flag for disabling the tsc */
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extern int tsc_disable;
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struct desc_struct {
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unsigned long a,b;
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};
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#define desc_empty(desc) \
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(!((desc)->a | (desc)->b))
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#define desc_equal(desc1, desc2) \
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(((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head.S, so think twice
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* before touching them. [mj]
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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char wp_works_ok; /* It doesn't on 386's */
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char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
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char hard_math;
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char rfu;
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int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
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unsigned long x86_capability[NCAPINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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int x86_cache_size; /* in KB - valid for CPUS which support this
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call */
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int x86_cache_alignment; /* In bytes */
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char fdiv_bug;
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char f00f_bug;
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char coma_bug;
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char pad0;
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int x86_power;
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unsigned long loops_per_jiffy;
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#ifdef CONFIG_SMP
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cpumask_t llc_shared_map; /* cpus sharing the last level cache */
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#endif
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unsigned char x86_max_cores; /* cpuid returned max cores value */
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unsigned char apicid;
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unsigned short x86_clflush_size;
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#ifdef CONFIG_SMP
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unsigned char booted_cores; /* number of cores as seen by OS */
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__u8 phys_proc_id; /* Physical processor id. */
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__u8 cpu_core_id; /* Core id */
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#endif
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} __attribute__((__aligned__(SMP_CACHE_BYTES)));
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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#ifdef CONFIG_SMP
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extern struct cpuinfo_x86 cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#else
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#define cpu_data (&boot_cpu_data)
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#define current_cpu_data boot_cpu_data
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#endif
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extern int cpu_llc_id[NR_CPUS];
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extern char ignore_fpu_irq;
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void __init cpu_detect(struct cpuinfo_x86 *c);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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#ifdef CONFIG_X86_HT
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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static inline void detect_ht(struct cpuinfo_x86 *c) {}
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#endif
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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}
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#define load_cr3(pgdir) write_cr3(__pa(pgdir))
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/*
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* Save the cr4 feature set we're using (ie
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* Pentium 4MB enable and PPro Global page
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* enable), so that any CPU's that boot up
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* after us can get the correct flags.
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*/
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extern unsigned long mmu_cr4_features;
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static inline void set_in_cr4 (unsigned long mask)
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{
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unsigned cr4;
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mmu_cr4_features |= mask;
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cr4 = read_cr4();
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cr4 |= mask;
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write_cr4(cr4);
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}
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static inline void clear_in_cr4 (unsigned long mask)
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{
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unsigned cr4;
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mmu_cr4_features &= ~mask;
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cr4 = read_cr4();
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cr4 &= ~mask;
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write_cr4(cr4);
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}
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/* Stop speculative execution */
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static inline void sync_core(void)
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{
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int tmp;
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asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
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}
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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{
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/* "monitor %eax,%ecx,%edx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc8;"
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: :"a" (eax), "c" (ecx), "d"(edx));
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}
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static inline void __mwait(unsigned long eax, unsigned long ecx)
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{
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/* "mwait %eax,%ecx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc9;"
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: :"a" (eax), "c" (ecx));
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}
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extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
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/* from system description table in BIOS. Mostly for MCA use, but
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others may find it useful. */
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extern unsigned int machine_id;
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extern unsigned int machine_submodel_id;
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extern unsigned int BIOS_revision;
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extern unsigned int mca_pentium_flag;
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/* Boot loader type from the setup header */
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extern int bootloader_type;
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/*
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* User space process size: 3GB (default).
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*/
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#define TASK_SIZE (PAGE_OFFSET)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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extern void hard_disable_TSC(void);
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extern void disable_TSC(void);
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extern void hard_enable_TSC(void);
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct i387_fsave_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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long status; /* software status information */
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};
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struct i387_fxsave_struct {
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unsigned short cwd;
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unsigned short swd;
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unsigned short twd;
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unsigned short fop;
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long fip;
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long fcs;
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long foo;
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long fos;
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long mxcsr;
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long mxcsr_mask;
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long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
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long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
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long padding[56];
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} __attribute__ ((aligned (16)));
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struct i387_soft_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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unsigned char ftop, changed, lookahead, no_update, rm, alimit;
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struct info *info;
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unsigned long entry_eip;
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};
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union i387_union {
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struct i387_fsave_struct fsave;
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struct i387_fxsave_struct fxsave;
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struct i387_soft_struct soft;
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};
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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struct thread_struct;
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/* This is the TSS defined by the hardware. */
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struct i386_hw_tss {
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unsigned short back_link,__blh;
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unsigned long esp0;
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unsigned short ss0,__ss0h;
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unsigned long esp1;
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unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
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unsigned long esp2;
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unsigned short ss2,__ss2h;
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unsigned long __cr3;
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unsigned long eip;
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unsigned long eflags;
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unsigned long eax,ecx,edx,ebx;
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unsigned long esp;
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unsigned long ebp;
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unsigned long esi;
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unsigned long edi;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace, io_bitmap_base;
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} __attribute__((packed));
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struct tss_struct {
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struct i386_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* pads the TSS to be cacheline-aligned (size is 0x100)
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*/
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unsigned long __cacheline_filler[35];
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/*
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* .. and then another 0x100 bytes for emergency kernel stack
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*/
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unsigned long stack[64];
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} __attribute__((packed));
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#define ARCH_MIN_TASKALIGN 16
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struct thread_struct {
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/* cached TLS descriptors. */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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unsigned long esp0;
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unsigned long sysenter_cs;
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unsigned long eip;
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unsigned long esp;
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unsigned long fs;
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unsigned long gs;
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/* Hardware debugging registers */
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unsigned long debugreg[8]; /* %%db0-7 debug registers */
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/* fault info */
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unsigned long cr2, trap_no, error_code;
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/* floating point info */
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union i387_union i387;
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/* virtual 86 mode info */
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struct vm86_struct __user * vm86_info;
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unsigned long screen_bitmap;
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unsigned long v86flags, v86mask, saved_esp0;
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unsigned int saved_fs, saved_gs;
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/* IO permissions */
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unsigned long *io_bitmap_ptr;
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unsigned long iopl;
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/* max allowed port in the bitmap, in bytes: */
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unsigned long io_bitmap_max;
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};
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#define INIT_THREAD { \
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.esp0 = sizeof(init_stack) + (long)&init_stack, \
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.vm86_info = NULL, \
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.sysenter_cs = __KERNEL_CS, \
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.io_bitmap_ptr = NULL, \
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.fs = __KERNEL_PERCPU, \
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}
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/*
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* Note that the .io_bitmap member must be extra-big. This is because
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* the CPU will access an additional byte beyond the end of the IO
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* permission bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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#define INIT_TSS { \
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.x86_tss = { \
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.esp0 = sizeof(init_stack) + (long)&init_stack, \
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.ss0 = __KERNEL_DS, \
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.ss1 = __KERNEL_CS, \
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
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}, \
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.io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
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}
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#define start_thread(regs, new_eip, new_esp) do { \
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__asm__("movl %0,%%gs": :"r" (0)); \
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regs->xfs = 0; \
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set_fs(USER_DS); \
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regs->xds = __USER_DS; \
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regs->xes = __USER_DS; \
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regs->xss = __USER_DS; \
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regs->xcs = __USER_CS; \
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regs->eip = new_eip; \
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regs->esp = new_esp; \
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} while (0)
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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/* Prepare to copy thread state - unlazy all lazy status */
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extern void prepare_to_copy(struct task_struct *tsk);
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/*
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* create a kernel thread without removing it from tasklists
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*/
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extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
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extern unsigned long thread_saved_pc(struct task_struct *tsk);
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void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
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unsigned long get_wchan(struct task_struct *p);
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#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
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#define KSTK_TOP(info) \
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({ \
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unsigned long *__ptr = (unsigned long *)(info); \
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(unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
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})
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/*
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* The below -8 is to reserve 8 bytes on top of the ring0 stack.
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* This is necessary to guarantee that the entire "struct pt_regs"
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* is accessable even if the CPU haven't stored the SS/ESP registers
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* on the stack (interrupt gate does not save these registers
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* when switching to the same priv ring).
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* Therefore beware: accessing the xss/esp fields of the
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* "struct pt_regs" is possible, but they may contain the
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* completely wrong values.
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*/
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#define task_pt_regs(task) \
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({ \
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struct pt_regs *__regs__; \
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__regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
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__regs__ - 1; \
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})
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#define KSTK_EIP(task) (task_pt_regs(task)->eip)
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#define KSTK_ESP(task) (task_pt_regs(task)->esp)
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struct microcode_header {
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unsigned int hdrver;
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unsigned int rev;
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unsigned int date;
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unsigned int sig;
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unsigned int cksum;
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unsigned int ldrver;
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unsigned int pf;
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unsigned int datasize;
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unsigned int totalsize;
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unsigned int reserved[3];
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};
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struct microcode {
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struct microcode_header hdr;
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unsigned int bits[0];
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};
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typedef struct microcode microcode_t;
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typedef struct microcode_header microcode_header_t;
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/* microcode format is extended from prescott processors */
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struct extended_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int cksum;
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};
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struct extended_sigtable {
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unsigned int count;
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unsigned int cksum;
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unsigned int reserved[3];
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struct extended_signature sigs[0];
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};
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/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
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static inline void rep_nop(void)
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{
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__asm__ __volatile__("rep;nop": : :"memory");
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}
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#define cpu_relax() rep_nop()
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static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
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{
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tss->x86_tss.esp0 = thread->esp0;
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/* This can only happen when SEP is enabled, no need to test "SEP"arately */
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if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
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tss->x86_tss.ss1 = thread->sysenter_cs;
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wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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}
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}
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static inline unsigned long native_get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("movl %%db0, %0" :"=r" (val)); break;
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case 1:
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asm("movl %%db1, %0" :"=r" (val)); break;
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case 2:
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asm("movl %%db2, %0" :"=r" (val)); break;
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case 3:
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asm("movl %%db3, %0" :"=r" (val)); break;
|
|
case 6:
|
|
asm("movl %%db6, %0" :"=r" (val)); break;
|
|
case 7:
|
|
asm("movl %%db7, %0" :"=r" (val)); break;
|
|
default:
|
|
BUG();
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static inline void native_set_debugreg(int regno, unsigned long value)
|
|
{
|
|
switch (regno) {
|
|
case 0:
|
|
asm("movl %0,%%db0" : /* no output */ :"r" (value));
|
|
break;
|
|
case 1:
|
|
asm("movl %0,%%db1" : /* no output */ :"r" (value));
|
|
break;
|
|
case 2:
|
|
asm("movl %0,%%db2" : /* no output */ :"r" (value));
|
|
break;
|
|
case 3:
|
|
asm("movl %0,%%db3" : /* no output */ :"r" (value));
|
|
break;
|
|
case 6:
|
|
asm("movl %0,%%db6" : /* no output */ :"r" (value));
|
|
break;
|
|
case 7:
|
|
asm("movl %0,%%db7" : /* no output */ :"r" (value));
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set IOPL bits in EFLAGS from given mask
|
|
*/
|
|
static inline void native_set_iopl_mask(unsigned mask)
|
|
{
|
|
unsigned int reg;
|
|
__asm__ __volatile__ ("pushfl;"
|
|
"popl %0;"
|
|
"andl %1, %0;"
|
|
"orl %2, %0;"
|
|
"pushl %0;"
|
|
"popfl"
|
|
: "=&r" (reg)
|
|
: "i" (~X86_EFLAGS_IOPL), "r" (mask));
|
|
}
|
|
|
|
#ifdef CONFIG_PARAVIRT
|
|
#include <asm/paravirt.h>
|
|
#else
|
|
#define paravirt_enabled() 0
|
|
#define __cpuid native_cpuid
|
|
|
|
static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
|
|
{
|
|
native_load_esp0(tss, thread);
|
|
}
|
|
|
|
/*
|
|
* These special macros can be used to get or set a debugging register
|
|
*/
|
|
#define get_debugreg(var, register) \
|
|
(var) = native_get_debugreg(register)
|
|
#define set_debugreg(value, register) \
|
|
native_set_debugreg(register, value)
|
|
|
|
#define set_iopl_mask native_set_iopl_mask
|
|
#endif /* CONFIG_PARAVIRT */
|
|
|
|
/*
|
|
* Generic CPUID function
|
|
* clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
|
|
* resulting in stale register contents being returned.
|
|
*/
|
|
static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = 0;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/* Some CPUID calls want 'count' to be placed in ecx */
|
|
static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
|
|
int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = count;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/*
|
|
* CPUID functions returning a single datum
|
|
*/
|
|
static inline unsigned int cpuid_eax(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return eax;
|
|
}
|
|
static inline unsigned int cpuid_ebx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return ebx;
|
|
}
|
|
static inline unsigned int cpuid_ecx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return ecx;
|
|
}
|
|
static inline unsigned int cpuid_edx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return edx;
|
|
}
|
|
|
|
/* generic versions from gas */
|
|
#define GENERIC_NOP1 ".byte 0x90\n"
|
|
#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
|
|
#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
|
|
#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
|
|
#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
|
|
#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
|
|
#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
|
|
#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
|
|
|
|
/* Opteron nops */
|
|
#define K8_NOP1 GENERIC_NOP1
|
|
#define K8_NOP2 ".byte 0x66,0x90\n"
|
|
#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
|
|
#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
|
|
#define K8_NOP5 K8_NOP3 K8_NOP2
|
|
#define K8_NOP6 K8_NOP3 K8_NOP3
|
|
#define K8_NOP7 K8_NOP4 K8_NOP3
|
|
#define K8_NOP8 K8_NOP4 K8_NOP4
|
|
|
|
/* K7 nops */
|
|
/* uses eax dependencies (arbitary choice) */
|
|
#define K7_NOP1 GENERIC_NOP1
|
|
#define K7_NOP2 ".byte 0x8b,0xc0\n"
|
|
#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
|
|
#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
|
|
#define K7_NOP5 K7_NOP4 ASM_NOP1
|
|
#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
|
|
#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
|
|
#define K7_NOP8 K7_NOP7 ASM_NOP1
|
|
|
|
#ifdef CONFIG_MK8
|
|
#define ASM_NOP1 K8_NOP1
|
|
#define ASM_NOP2 K8_NOP2
|
|
#define ASM_NOP3 K8_NOP3
|
|
#define ASM_NOP4 K8_NOP4
|
|
#define ASM_NOP5 K8_NOP5
|
|
#define ASM_NOP6 K8_NOP6
|
|
#define ASM_NOP7 K8_NOP7
|
|
#define ASM_NOP8 K8_NOP8
|
|
#elif defined(CONFIG_MK7)
|
|
#define ASM_NOP1 K7_NOP1
|
|
#define ASM_NOP2 K7_NOP2
|
|
#define ASM_NOP3 K7_NOP3
|
|
#define ASM_NOP4 K7_NOP4
|
|
#define ASM_NOP5 K7_NOP5
|
|
#define ASM_NOP6 K7_NOP6
|
|
#define ASM_NOP7 K7_NOP7
|
|
#define ASM_NOP8 K7_NOP8
|
|
#else
|
|
#define ASM_NOP1 GENERIC_NOP1
|
|
#define ASM_NOP2 GENERIC_NOP2
|
|
#define ASM_NOP3 GENERIC_NOP3
|
|
#define ASM_NOP4 GENERIC_NOP4
|
|
#define ASM_NOP5 GENERIC_NOP5
|
|
#define ASM_NOP6 GENERIC_NOP6
|
|
#define ASM_NOP7 GENERIC_NOP7
|
|
#define ASM_NOP8 GENERIC_NOP8
|
|
#endif
|
|
|
|
#define ASM_NOP_MAX 8
|
|
|
|
/* Prefetch instructions for Pentium III and AMD Athlon */
|
|
/* It's not worth to care about 3dnow! prefetches for the K6
|
|
because they are microcoded there and very slow.
|
|
However we don't do prefetches for pre XP Athlons currently
|
|
That should be fixed. */
|
|
#define ARCH_HAS_PREFETCH
|
|
static inline void prefetch(const void *x)
|
|
{
|
|
alternative_input(ASM_NOP4,
|
|
"prefetchnta (%1)",
|
|
X86_FEATURE_XMM,
|
|
"r" (x));
|
|
}
|
|
|
|
#define ARCH_HAS_PREFETCH
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
/* 3dnow! prefetch to get an exclusive cache line. Useful for
|
|
spinlocks to avoid one state transition in the cache coherency protocol. */
|
|
static inline void prefetchw(const void *x)
|
|
{
|
|
alternative_input(ASM_NOP4,
|
|
"prefetchw (%1)",
|
|
X86_FEATURE_3DNOW,
|
|
"r" (x));
|
|
}
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
|
|
extern void select_idle_routine(const struct cpuinfo_x86 *c);
|
|
|
|
#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
extern void enable_sep_cpu(void);
|
|
extern int sysenter_setup(void);
|
|
|
|
/* Defined in head.S */
|
|
extern struct Xgt_desc_struct early_gdt_descr;
|
|
|
|
extern void cpu_set_gdt(int);
|
|
extern void switch_to_new_gdt(void);
|
|
extern void cpu_init(void);
|
|
extern void init_gdt(int cpu);
|
|
|
|
extern int force_mwait;
|
|
|
|
#endif /* __ASM_I386_PROCESSOR_H */
|