299 lines
8.1 KiB
C
299 lines
8.1 KiB
C
/*
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* Firmware replacement code.
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*
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* Work around broken BIOSes that don't set an aperture or only set the
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* aperture in the AGP bridge.
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* If all fails map the aperture over some low memory. This is cheaper than
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* doing bounce buffering. The memory is lost. This is done at early boot
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* because only the bootmem allocator can allocate 32+MB.
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*
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* Copyright 2002 Andi Kleen, SuSE Labs.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mmzone.h>
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#include <linux/pci_ids.h>
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#include <linux/pci.h>
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#include <linux/bitops.h>
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#include <linux/ioport.h>
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#include <asm/e820.h>
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#include <asm/io.h>
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#include <asm/iommu.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/k8.h>
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int iommu_aperture;
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int iommu_aperture_disabled __initdata = 0;
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int iommu_aperture_allowed __initdata = 0;
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int fallback_aper_order __initdata = 1; /* 64MB */
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int fallback_aper_force __initdata = 0;
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int fix_aperture __initdata = 1;
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static struct resource gart_resource = {
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.name = "GART",
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.flags = IORESOURCE_MEM,
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};
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static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
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{
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gart_resource.start = aper_base;
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gart_resource.end = aper_base + aper_size - 1;
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insert_resource(&iomem_resource, &gart_resource);
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}
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/* This code runs before the PCI subsystem is initialized, so just
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access the northbridge directly. */
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static u32 __init allocate_aperture(void)
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{
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u32 aper_size;
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void *p;
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if (fallback_aper_order > 7)
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fallback_aper_order = 7;
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aper_size = (32 * 1024 * 1024) << fallback_aper_order;
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/*
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* Aperture has to be naturally aligned. This means an 2GB aperture won't
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* have much chance of finding a place in the lower 4GB of memory.
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* Unfortunately we cannot move it up because that would make the
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* IOMMU useless.
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*/
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p = __alloc_bootmem_nopanic(aper_size, aper_size, 0);
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if (!p || __pa(p)+aper_size > 0xffffffff) {
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printk("Cannot allocate aperture memory hole (%p,%uK)\n",
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p, aper_size>>10);
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if (p)
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free_bootmem(__pa(p), aper_size);
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return 0;
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}
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printk("Mapping aperture over %d KB of RAM @ %lx\n",
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aper_size >> 10, __pa(p));
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insert_aperture_resource((u32)__pa(p), aper_size);
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return (u32)__pa(p);
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}
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static int __init aperture_valid(u64 aper_base, u32 aper_size)
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{
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if (!aper_base)
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return 0;
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if (aper_size < 64*1024*1024) {
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printk("Aperture too small (%d MB)\n", aper_size>>20);
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return 0;
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}
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if (aper_base + aper_size > 0x100000000UL) {
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printk("Aperture beyond 4GB. Ignoring.\n");
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return 0;
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}
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if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
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printk("Aperture pointing to e820 RAM. Ignoring.\n");
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return 0;
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}
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return 1;
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}
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/* Find a PCI capability */
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static __u32 __init find_cap(int num, int slot, int func, int cap)
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{
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u8 pos;
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int bytes;
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if (!(read_pci_config_16(num,slot,func,PCI_STATUS) & PCI_STATUS_CAP_LIST))
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return 0;
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pos = read_pci_config_byte(num,slot,func,PCI_CAPABILITY_LIST);
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for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
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u8 id;
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pos &= ~3;
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id = read_pci_config_byte(num,slot,func,pos+PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos = read_pci_config_byte(num,slot,func,pos+PCI_CAP_LIST_NEXT);
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}
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return 0;
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}
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/* Read a standard AGPv3 bridge header */
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static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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{
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u32 apsize;
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u32 apsizereg;
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int nbits;
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u32 aper_low, aper_hi;
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u64 aper;
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printk("AGP bridge at %02x:%02x:%02x\n", num, slot, func);
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apsizereg = read_pci_config_16(num,slot,func, cap + 0x14);
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if (apsizereg == 0xffffffff) {
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printk("APSIZE in AGP bridge unreadable\n");
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return 0;
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}
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apsize = apsizereg & 0xfff;
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/* Some BIOS use weird encodings not in the AGPv3 table. */
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if (apsize & 0xff)
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apsize |= 0xf00;
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nbits = hweight16(apsize);
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*order = 7 - nbits;
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if ((int)*order < 0) /* < 32MB */
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*order = 0;
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aper_low = read_pci_config(num,slot,func, 0x10);
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aper_hi = read_pci_config(num,slot,func,0x14);
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aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
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printk("Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
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aper, 32 << *order, apsizereg);
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if (!aperture_valid(aper, (32*1024*1024) << *order))
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return 0;
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return (u32)aper;
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}
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/* Look for an AGP bridge. Windows only expects the aperture in the
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AGP bridge and some BIOS forget to initialize the Northbridge too.
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Work around this here.
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Do an PCI bus scan by hand because we're running before the PCI
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subsystem.
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All K8 AGP bridges are AGPv3 compliant, so we can do this scan
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generically. It's probably overkill to always scan all slots because
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the AGP bridges should be always an own bus on the HT hierarchy,
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but do it here for future safety. */
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static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
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{
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int num, slot, func;
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/* Poor man's PCI discovery */
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for (num = 0; num < 256; num++) {
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for (slot = 0; slot < 32; slot++) {
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for (func = 0; func < 8; func++) {
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u32 class, cap;
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u8 type;
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class = read_pci_config(num,slot,func,
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PCI_CLASS_REVISION);
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if (class == 0xffffffff)
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break;
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switch (class >> 16) {
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case PCI_CLASS_BRIDGE_HOST:
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case PCI_CLASS_BRIDGE_OTHER: /* needed? */
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/* AGP bridge? */
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cap = find_cap(num,slot,func,PCI_CAP_ID_AGP);
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if (!cap)
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break;
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*valid_agp = 1;
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return read_agp(num,slot,func,cap,order);
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}
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/* No multi-function device? */
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type = read_pci_config_byte(num,slot,func,
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PCI_HEADER_TYPE);
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if (!(type & 0x80))
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break;
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}
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}
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}
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printk("No AGP bridge found\n");
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return 0;
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}
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void __init iommu_hole_init(void)
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{
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int fix, num;
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u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
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u64 aper_base, last_aper_base = 0;
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int valid_agp = 0;
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if (iommu_aperture_disabled || !fix_aperture || !early_pci_allowed())
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return;
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printk(KERN_INFO "Checking aperture...\n");
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fix = 0;
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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iommu_detected = 1;
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iommu_aperture = 1;
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aper_order = (read_pci_config(0, num, 3, 0x90) >> 1) & 7;
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aper_size = (32 * 1024 * 1024) << aper_order;
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aper_base = read_pci_config(0, num, 3, 0x94) & 0x7fff;
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aper_base <<= 25;
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printk("CPU %d: aperture @ %Lx size %u MB\n", num-24,
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aper_base, aper_size>>20);
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if (!aperture_valid(aper_base, aper_size)) {
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fix = 1;
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break;
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}
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if ((last_aper_order && aper_order != last_aper_order) ||
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(last_aper_base && aper_base != last_aper_base)) {
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fix = 1;
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break;
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}
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last_aper_order = aper_order;
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last_aper_base = aper_base;
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}
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if (!fix && !fallback_aper_force) {
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if (last_aper_base) {
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unsigned long n = (32 * 1024 * 1024) << last_aper_order;
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insert_aperture_resource((u32)last_aper_base, n);
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}
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return;
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}
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if (!fallback_aper_force)
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aper_alloc = search_agp_bridge(&aper_order, &valid_agp);
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if (aper_alloc) {
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/* Got the aperture from the AGP bridge */
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} else if (swiotlb && !valid_agp) {
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/* Do nothing */
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} else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
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force_iommu ||
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valid_agp ||
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fallback_aper_force) {
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printk("Your BIOS doesn't leave a aperture memory hole\n");
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printk("Please enable the IOMMU option in the BIOS setup\n");
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printk("This costs you %d MB of RAM\n",
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32 << fallback_aper_order);
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aper_order = fallback_aper_order;
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aper_alloc = allocate_aperture();
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if (!aper_alloc) {
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/* Could disable AGP and IOMMU here, but it's probably
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not worth it. But the later users cannot deal with
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bad apertures and turning on the aperture over memory
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causes very strange problems, so it's better to
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panic early. */
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panic("Not enough memory for aperture");
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}
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} else {
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return;
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}
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/* Fix up the north bridges */
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for (num = 24; num < 32; num++) {
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if (!early_is_k8_nb(read_pci_config(0, num, 3, 0x00)))
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continue;
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/* Don't enable translation yet. That is done later.
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Assume this BIOS didn't initialise the GART so
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just overwrite all previous bits */
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write_pci_config(0, num, 3, 0x90, aper_order<<1);
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write_pci_config(0, num, 3, 0x94, aper_alloc>>25);
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}
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}
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