132 lines
3.9 KiB
C
132 lines
3.9 KiB
C
/*
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* File: arch/blackfin/mach-bf561/dma.c
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* Based on:
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* Author:
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*
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* Created:
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* Description: This file contains the simple DMA Implementation for Blackfin
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
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(struct dma_register *) DMA1_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_2_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_3_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_4_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_5_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_6_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_7_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_8_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_9_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_10_NEXT_DESC_PTR,
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(struct dma_register *) DMA1_11_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_0_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_1_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_2_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_3_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_4_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_5_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_6_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_7_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_8_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_9_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_10_NEXT_DESC_PTR,
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(struct dma_register *) DMA2_11_NEXT_DESC_PTR,
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(struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
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(struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
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(struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
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(struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
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};
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int channel2irq(unsigned int channel)
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{
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int ret_irq = -1;
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switch (channel) {
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case CH_PPI0:
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ret_irq = IRQ_PPI0;
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break;
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case CH_PPI1:
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ret_irq = IRQ_PPI1;
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break;
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case CH_SPORT0_RX:
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ret_irq = IRQ_SPORT0_RX;
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break;
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case CH_SPORT0_TX:
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ret_irq = IRQ_SPORT0_TX;
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break;
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case CH_SPORT1_RX:
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ret_irq = IRQ_SPORT1_RX;
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break;
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case CH_SPORT1_TX:
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ret_irq = IRQ_SPORT1_TX;
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break;
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case CH_SPI:
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ret_irq = IRQ_SPI;
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break;
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case CH_UART_RX:
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ret_irq = IRQ_UART_RX;
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break;
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case CH_UART_TX:
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ret_irq = IRQ_UART_TX;
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break;
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case CH_MEM_STREAM0_SRC:
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case CH_MEM_STREAM0_DEST:
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ret_irq = IRQ_MEM_DMA0;
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break;
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case CH_MEM_STREAM1_SRC:
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case CH_MEM_STREAM1_DEST:
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ret_irq = IRQ_MEM_DMA1;
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break;
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case CH_MEM_STREAM2_SRC:
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case CH_MEM_STREAM2_DEST:
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ret_irq = IRQ_MEM_DMA2;
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break;
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case CH_MEM_STREAM3_SRC:
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case CH_MEM_STREAM3_DEST:
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ret_irq = IRQ_MEM_DMA3;
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break;
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case CH_IMEM_STREAM0_SRC:
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case CH_IMEM_STREAM0_DEST:
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ret_irq = IRQ_IMEM_DMA0;
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break;
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case CH_IMEM_STREAM1_SRC:
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case CH_IMEM_STREAM1_DEST:
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ret_irq = IRQ_IMEM_DMA1;
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break;
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}
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return ret_irq;
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}
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