570 lines
16 KiB
C
570 lines
16 KiB
C
/*
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* PTP 1588 clock using the eTSEC
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*
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* Copyright (C) 2010 OMICRON electronics GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/device.h>
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#include <linux/hrtimer.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/timex.h>
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#include <linux/io.h>
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#include <linux/ptp_clock_kernel.h>
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#include "gianfar.h"
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/*
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* gianfar ptp registers
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* Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
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*/
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struct gianfar_ptp_registers {
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u32 tmr_ctrl; /* Timer control register */
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u32 tmr_tevent; /* Timestamp event register */
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u32 tmr_temask; /* Timer event mask register */
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u32 tmr_pevent; /* Timestamp event register */
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u32 tmr_pemask; /* Timer event mask register */
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u32 tmr_stat; /* Timestamp status register */
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u32 tmr_cnt_h; /* Timer counter high register */
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u32 tmr_cnt_l; /* Timer counter low register */
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u32 tmr_add; /* Timer drift compensation addend register */
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u32 tmr_acc; /* Timer accumulator register */
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u32 tmr_prsc; /* Timer prescale */
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u8 res1[4];
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u32 tmroff_h; /* Timer offset high */
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u32 tmroff_l; /* Timer offset low */
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u8 res2[8];
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u32 tmr_alarm1_h; /* Timer alarm 1 high register */
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u32 tmr_alarm1_l; /* Timer alarm 1 high register */
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u32 tmr_alarm2_h; /* Timer alarm 2 high register */
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u32 tmr_alarm2_l; /* Timer alarm 2 high register */
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u8 res3[48];
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u32 tmr_fiper1; /* Timer fixed period interval */
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u32 tmr_fiper2; /* Timer fixed period interval */
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u32 tmr_fiper3; /* Timer fixed period interval */
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u8 res4[20];
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u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
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};
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/* Bit definitions for the TMR_CTRL register */
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#define ALM1P (1<<31) /* Alarm1 output polarity */
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#define ALM2P (1<<30) /* Alarm2 output polarity */
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#define FS (1<<28) /* FIPER start indication */
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#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
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#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
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#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
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#define TCLK_PERIOD_MASK (0x3ff)
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#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
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#define FRD (1<<14) /* FIPER Realignment Disable */
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#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
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#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
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#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
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#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
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#define COPH (1<<7) /* Generated clock output phase. */
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#define CIPH (1<<6) /* External oscillator input clock phase */
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#define TMSR (1<<5) /* Timer soft reset. */
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#define BYP (1<<3) /* Bypass drift compensated clock */
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#define TE (1<<2) /* 1588 timer enable. */
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#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
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#define CKSEL_MASK (0x3)
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/* Bit definitions for the TMR_TEVENT register */
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#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
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#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
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#define ALM2 (1<<17) /* Current time = alarm time register 2 */
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#define ALM1 (1<<16) /* Current time = alarm time register 1 */
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#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
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#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
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#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
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/* Bit definitions for the TMR_TEMASK register */
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#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
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#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
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#define ALM2EN (1<<17) /* Timer ALM2 event enable */
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#define ALM1EN (1<<16) /* Timer ALM1 event enable */
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#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
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#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
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/* Bit definitions for the TMR_PEVENT register */
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#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
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#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
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#define RXP (1<<0) /* PTP frame has been received */
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/* Bit definitions for the TMR_PEMASK register */
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#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
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#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
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#define RXPEN (1<<0) /* Receive PTP packet event enable */
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/* Bit definitions for the TMR_STAT register */
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#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
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#define STAT_VEC_MASK (0x3f)
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/* Bit definitions for the TMR_PRSC register */
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#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
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#define PRSC_OCK_MASK (0xffff)
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#define DRIVER "gianfar_ptp"
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#define DEFAULT_CKSEL 1
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#define N_ALARM 1 /* first alarm is used internally to reset fipers */
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#define N_EXT_TS 2
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#define REG_SIZE sizeof(struct gianfar_ptp_registers)
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struct etsects {
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struct gianfar_ptp_registers *regs;
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spinlock_t lock; /* protects regs */
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struct ptp_clock *clock;
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struct ptp_clock_info caps;
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struct resource *rsrc;
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int irq;
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u64 alarm_interval; /* for periodic alarm */
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u64 alarm_value;
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u32 tclk_period; /* nanoseconds */
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u32 tmr_prsc;
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u32 tmr_add;
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u32 cksel;
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u32 tmr_fiper1;
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u32 tmr_fiper2;
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};
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/*
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* Register access functions
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*/
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/* Caller must hold etsects->lock. */
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static u64 tmr_cnt_read(struct etsects *etsects)
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{
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u64 ns;
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u32 lo, hi;
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lo = gfar_read(&etsects->regs->tmr_cnt_l);
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hi = gfar_read(&etsects->regs->tmr_cnt_h);
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ns = ((u64) hi) << 32;
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ns |= lo;
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return ns;
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}
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/* Caller must hold etsects->lock. */
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static void tmr_cnt_write(struct etsects *etsects, u64 ns)
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{
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u32 hi = ns >> 32;
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u32 lo = ns & 0xffffffff;
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gfar_write(&etsects->regs->tmr_cnt_l, lo);
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gfar_write(&etsects->regs->tmr_cnt_h, hi);
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}
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/* Caller must hold etsects->lock. */
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static void set_alarm(struct etsects *etsects)
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{
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u64 ns;
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u32 lo, hi;
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ns = tmr_cnt_read(etsects) + 1500000000ULL;
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ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
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ns -= etsects->tclk_period;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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gfar_write(&etsects->regs->tmr_alarm1_l, lo);
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gfar_write(&etsects->regs->tmr_alarm1_h, hi);
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}
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/* Caller must hold etsects->lock. */
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static void set_fipers(struct etsects *etsects)
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{
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set_alarm(etsects);
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gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
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gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
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}
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/*
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* Interrupt service routine
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*/
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static irqreturn_t isr(int irq, void *priv)
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{
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struct etsects *etsects = priv;
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struct ptp_clock_event event;
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u64 ns;
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u32 ack = 0, lo, hi, mask, val;
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val = gfar_read(&etsects->regs->tmr_tevent);
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if (val & ETS1) {
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ack |= ETS1;
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hi = gfar_read(&etsects->regs->tmr_etts1_h);
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lo = gfar_read(&etsects->regs->tmr_etts1_l);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 0;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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ptp_clock_event(etsects->clock, &event);
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}
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if (val & ETS2) {
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ack |= ETS2;
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hi = gfar_read(&etsects->regs->tmr_etts2_h);
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lo = gfar_read(&etsects->regs->tmr_etts2_l);
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event.type = PTP_CLOCK_EXTTS;
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event.index = 1;
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event.timestamp = ((u64) hi) << 32;
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event.timestamp |= lo;
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ptp_clock_event(etsects->clock, &event);
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}
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if (val & ALM2) {
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ack |= ALM2;
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if (etsects->alarm_value) {
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event.type = PTP_CLOCK_ALARM;
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event.index = 0;
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event.timestamp = etsects->alarm_value;
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ptp_clock_event(etsects->clock, &event);
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}
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if (etsects->alarm_interval) {
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ns = etsects->alarm_value + etsects->alarm_interval;
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hi = ns >> 32;
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lo = ns & 0xffffffff;
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spin_lock(&etsects->lock);
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gfar_write(&etsects->regs->tmr_alarm2_l, lo);
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gfar_write(&etsects->regs->tmr_alarm2_h, hi);
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spin_unlock(&etsects->lock);
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etsects->alarm_value = ns;
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} else {
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gfar_write(&etsects->regs->tmr_tevent, ALM2);
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spin_lock(&etsects->lock);
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mask = gfar_read(&etsects->regs->tmr_temask);
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mask &= ~ALM2EN;
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gfar_write(&etsects->regs->tmr_temask, mask);
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spin_unlock(&etsects->lock);
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etsects->alarm_value = 0;
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etsects->alarm_interval = 0;
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}
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}
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if (val & PP1) {
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ack |= PP1;
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event.type = PTP_CLOCK_PPS;
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ptp_clock_event(etsects->clock, &event);
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}
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if (ack) {
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gfar_write(&etsects->regs->tmr_tevent, ack);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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/*
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* PTP clock operations
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*/
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static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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{
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u64 adj;
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u32 diff, tmr_add;
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int neg_adj = 0;
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struct etsects *etsects = container_of(ptp, struct etsects, caps);
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if (ppb < 0) {
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neg_adj = 1;
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ppb = -ppb;
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}
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tmr_add = etsects->tmr_add;
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adj = tmr_add;
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adj *= ppb;
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diff = div_u64(adj, 1000000000ULL);
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tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
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gfar_write(&etsects->regs->tmr_add, tmr_add);
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return 0;
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}
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static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
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{
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s64 now;
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unsigned long flags;
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struct etsects *etsects = container_of(ptp, struct etsects, caps);
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spin_lock_irqsave(&etsects->lock, flags);
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now = tmr_cnt_read(etsects);
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now += delta;
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tmr_cnt_write(etsects, now);
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spin_unlock_irqrestore(&etsects->lock, flags);
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set_fipers(etsects);
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return 0;
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}
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static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
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{
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u64 ns;
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u32 remainder;
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unsigned long flags;
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struct etsects *etsects = container_of(ptp, struct etsects, caps);
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spin_lock_irqsave(&etsects->lock, flags);
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ns = tmr_cnt_read(etsects);
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spin_unlock_irqrestore(&etsects->lock, flags);
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ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
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ts->tv_nsec = remainder;
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return 0;
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}
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static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
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const struct timespec *ts)
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{
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u64 ns;
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unsigned long flags;
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struct etsects *etsects = container_of(ptp, struct etsects, caps);
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ns = ts->tv_sec * 1000000000ULL;
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ns += ts->tv_nsec;
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spin_lock_irqsave(&etsects->lock, flags);
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tmr_cnt_write(etsects, ns);
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set_fipers(etsects);
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spin_unlock_irqrestore(&etsects->lock, flags);
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return 0;
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}
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static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
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struct ptp_clock_request *rq, int on)
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{
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struct etsects *etsects = container_of(ptp, struct etsects, caps);
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unsigned long flags;
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u32 bit, mask;
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switch (rq->type) {
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case PTP_CLK_REQ_EXTTS:
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switch (rq->extts.index) {
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case 0:
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bit = ETS1EN;
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break;
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case 1:
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bit = ETS2EN;
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break;
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default:
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return -EINVAL;
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}
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spin_lock_irqsave(&etsects->lock, flags);
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mask = gfar_read(&etsects->regs->tmr_temask);
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if (on)
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mask |= bit;
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else
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mask &= ~bit;
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gfar_write(&etsects->regs->tmr_temask, mask);
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spin_unlock_irqrestore(&etsects->lock, flags);
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return 0;
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case PTP_CLK_REQ_PPS:
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spin_lock_irqsave(&etsects->lock, flags);
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mask = gfar_read(&etsects->regs->tmr_temask);
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if (on)
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mask |= PP1EN;
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else
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mask &= ~PP1EN;
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gfar_write(&etsects->regs->tmr_temask, mask);
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spin_unlock_irqrestore(&etsects->lock, flags);
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return 0;
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default:
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break;
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}
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return -EOPNOTSUPP;
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}
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static struct ptp_clock_info ptp_gianfar_caps = {
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.owner = THIS_MODULE,
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.name = "gianfar clock",
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.max_adj = 512000,
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.n_alarm = N_ALARM,
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.n_ext_ts = N_EXT_TS,
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.n_per_out = 0,
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.pps = 1,
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.adjfreq = ptp_gianfar_adjfreq,
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.adjtime = ptp_gianfar_adjtime,
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.gettime = ptp_gianfar_gettime,
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.settime = ptp_gianfar_settime,
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.enable = ptp_gianfar_enable,
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};
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/* OF device tree */
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static int get_of_u32(struct device_node *node, char *str, u32 *val)
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{
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int plen;
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const u32 *prop = of_get_property(node, str, &plen);
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if (!prop || plen != sizeof(*prop))
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return -1;
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*val = *prop;
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return 0;
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}
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static int gianfar_ptp_probe(struct platform_device *dev)
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{
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struct device_node *node = dev->dev.of_node;
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struct etsects *etsects;
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struct timespec now;
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int err = -ENOMEM;
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u32 tmr_ctrl;
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unsigned long flags;
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etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
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if (!etsects)
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goto no_memory;
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err = -ENODEV;
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etsects->caps = ptp_gianfar_caps;
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etsects->cksel = DEFAULT_CKSEL;
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if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
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get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
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get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
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get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
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get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
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get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
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pr_err("device tree node missing required elements\n");
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goto no_node;
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}
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etsects->irq = platform_get_irq(dev, 0);
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if (etsects->irq == NO_IRQ) {
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pr_err("irq not in device tree\n");
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goto no_node;
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}
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if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
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pr_err("request_irq failed\n");
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goto no_node;
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}
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etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!etsects->rsrc) {
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pr_err("no resource\n");
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goto no_resource;
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}
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if (request_resource(&ioport_resource, etsects->rsrc)) {
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pr_err("resource busy\n");
|
|
goto no_resource;
|
|
}
|
|
|
|
spin_lock_init(&etsects->lock);
|
|
|
|
etsects->regs = ioremap(etsects->rsrc->start,
|
|
resource_size(etsects->rsrc));
|
|
if (!etsects->regs) {
|
|
pr_err("ioremap ptp registers failed\n");
|
|
goto no_ioremap;
|
|
}
|
|
getnstimeofday(&now);
|
|
ptp_gianfar_settime(&etsects->caps, &now);
|
|
|
|
tmr_ctrl =
|
|
(etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
|
|
(etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
|
|
|
|
spin_lock_irqsave(&etsects->lock, flags);
|
|
|
|
gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
|
|
gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
|
|
gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
|
|
gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
|
|
gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
|
|
set_alarm(etsects);
|
|
gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE|FRD);
|
|
|
|
spin_unlock_irqrestore(&etsects->lock, flags);
|
|
|
|
etsects->clock = ptp_clock_register(&etsects->caps);
|
|
if (IS_ERR(etsects->clock)) {
|
|
err = PTR_ERR(etsects->clock);
|
|
goto no_clock;
|
|
}
|
|
|
|
dev_set_drvdata(&dev->dev, etsects);
|
|
|
|
return 0;
|
|
|
|
no_clock:
|
|
no_ioremap:
|
|
release_resource(etsects->rsrc);
|
|
no_resource:
|
|
free_irq(etsects->irq, etsects);
|
|
no_node:
|
|
kfree(etsects);
|
|
no_memory:
|
|
return err;
|
|
}
|
|
|
|
static int gianfar_ptp_remove(struct platform_device *dev)
|
|
{
|
|
struct etsects *etsects = dev_get_drvdata(&dev->dev);
|
|
|
|
gfar_write(&etsects->regs->tmr_temask, 0);
|
|
gfar_write(&etsects->regs->tmr_ctrl, 0);
|
|
|
|
ptp_clock_unregister(etsects->clock);
|
|
iounmap(etsects->regs);
|
|
release_resource(etsects->rsrc);
|
|
free_irq(etsects->irq, etsects);
|
|
kfree(etsects);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id match_table[] = {
|
|
{ .compatible = "fsl,etsec-ptp" },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver gianfar_ptp_driver = {
|
|
.driver = {
|
|
.name = "gianfar_ptp",
|
|
.of_match_table = match_table,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.probe = gianfar_ptp_probe,
|
|
.remove = gianfar_ptp_remove,
|
|
};
|
|
|
|
module_platform_driver(gianfar_ptp_driver);
|
|
|
|
MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
|
|
MODULE_DESCRIPTION("PTP clock using the eTSEC");
|
|
MODULE_LICENSE("GPL");
|