486 lines
13 KiB
C
486 lines
13 KiB
C
/*
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* AMD64 class Memory Controller kernel module
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*
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* Copyright (c) 2009 SoftwareBitMaker.
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* Copyright (c) 2009-15 Advanced Micro Devices, Inc.
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*
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*/
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#include <linux/module.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include <linux/mmzone.h>
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#include <linux/edac.h>
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#include <asm/msr.h>
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#include "edac_core.h"
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#include "mce_amd.h"
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#define amd64_debug(fmt, arg...) \
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edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
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#define amd64_info(fmt, arg...) \
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edac_printk(KERN_INFO, "amd64", fmt, ##arg)
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#define amd64_notice(fmt, arg...) \
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edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
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#define amd64_warn(fmt, arg...) \
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edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
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#define amd64_err(fmt, arg...) \
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edac_printk(KERN_ERR, "amd64", fmt, ##arg)
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#define amd64_mc_warn(mci, fmt, arg...) \
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edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
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#define amd64_mc_err(mci, fmt, arg...) \
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edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
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/*
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* Throughout the comments in this code, the following terms are used:
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*
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* SysAddr, DramAddr, and InputAddr
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*
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* These terms come directly from the amd64 documentation
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* (AMD publication #26094). They are defined as follows:
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*
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* SysAddr:
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* This is a physical address generated by a CPU core or a device
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* doing DMA. If generated by a CPU core, a SysAddr is the result of
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* a virtual to physical address translation by the CPU core's address
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* translation mechanism (MMU).
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*
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* DramAddr:
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* A DramAddr is derived from a SysAddr by subtracting an offset that
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* depends on which node the SysAddr maps to and whether the SysAddr
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* is within a range affected by memory hoisting. The DRAM Base
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* (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
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* determine which node a SysAddr maps to.
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*
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* If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
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* is within the range of addresses specified by this register, then
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* a value x from the DHAR is subtracted from the SysAddr to produce a
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* DramAddr. Here, x represents the base address for the node that
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* the SysAddr maps to plus an offset due to memory hoisting. See
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* section 3.4.8 and the comments in amd64_get_dram_hole_info() and
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* sys_addr_to_dram_addr() below for more information.
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*
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* If the SysAddr is not affected by the DHAR then a value y is
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* subtracted from the SysAddr to produce a DramAddr. Here, y is the
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* base address for the node that the SysAddr maps to. See section
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* 3.4.4 and the comments in sys_addr_to_dram_addr() below for more
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* information.
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*
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* InputAddr:
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* A DramAddr is translated to an InputAddr before being passed to the
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* memory controller for the node that the DramAddr is associated
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* with. The memory controller then maps the InputAddr to a csrow.
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* If node interleaving is not in use, then the InputAddr has the same
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* value as the DramAddr. Otherwise, the InputAddr is produced by
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* discarding the bits used for node interleaving from the DramAddr.
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* See section 3.4.4 for more information.
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*
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* The memory controller for a given node uses its DRAM CS Base and
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* DRAM CS Mask registers to map an InputAddr to a csrow. See
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* sections 3.5.4 and 3.5.5 for more information.
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*/
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#define EDAC_AMD64_VERSION "3.4.0"
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#define EDAC_MOD_STR "amd64_edac"
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/* Extended Model from CPUID, for CPU Revision numbers */
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#define K8_REV_D 1
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#define K8_REV_E 2
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#define K8_REV_F 4
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/* Hardware limit on ChipSelect rows per MC and processors per system */
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#define NUM_CHIPSELECTS 8
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#define DRAM_RANGES 8
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#define ON true
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#define OFF false
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/*
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* PCI-defined configuration space registers
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*/
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#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
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#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
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#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
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#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
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#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
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#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
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#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
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#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
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#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
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/*
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* Function 1 - Address Map
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*/
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#define DRAM_BASE_LO 0x40
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#define DRAM_LIMIT_LO 0x44
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/*
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* F15 M30h D18F1x2[1C:00]
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*/
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#define DRAM_CONT_BASE 0x200
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#define DRAM_CONT_LIMIT 0x204
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/*
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* F15 M30h D18F1x2[4C:40]
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*/
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#define DRAM_CONT_HIGH_OFF 0x240
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#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
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#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
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#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
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#define DHAR 0xf0
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#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
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#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
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#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
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/* NOTE: Extra mask bit vs K8 */
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#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
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#define DCT_CFG_SEL 0x10C
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#define DRAM_LOCAL_NODE_BASE 0x120
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#define DRAM_LOCAL_NODE_LIM 0x124
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#define DRAM_BASE_HI 0x140
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#define DRAM_LIMIT_HI 0x144
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/*
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* Function 2 - DRAM controller
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*/
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#define DCSB0 0x40
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#define DCSB1 0x140
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#define DCSB_CS_ENABLE BIT(0)
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#define DCSM0 0x60
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#define DCSM1 0x160
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#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
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#define DRAM_CONTROL 0x78
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#define DBAM0 0x80
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#define DBAM1 0x180
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/* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */
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#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
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#define DBAM_MAX_VALUE 11
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#define DCLR0 0x90
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#define DCLR1 0x190
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#define REVE_WIDTH_128 BIT(16)
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#define WIDTH_128 BIT(11)
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#define DCHR0 0x94
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#define DCHR1 0x194
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#define DDR3_MODE BIT(8)
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#define DCT_SEL_LO 0x110
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#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
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#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
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#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
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#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
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#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
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#define SWAP_INTLV_REG 0x10c
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#define DCT_SEL_HI 0x114
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#define F15H_M60H_SCRCTRL 0x1C8
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/*
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* Function 3 - Misc Control
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*/
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#define NBCTL 0x40
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#define NBCFG 0x44
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#define NBCFG_CHIPKILL BIT(23)
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#define NBCFG_ECC_ENABLE BIT(22)
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/* F3x48: NBSL */
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#define F10_NBSL_EXT_ERR_ECC 0x8
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#define NBSL_PP_OBS 0x2
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#define SCRCTRL 0x58
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#define F10_ONLINE_SPARE 0xB0
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#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
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#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
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#define F10_NB_ARRAY_ADDR 0xB8
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#define F10_NB_ARRAY_DRAM BIT(31)
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/* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
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#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
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#define F10_NB_ARRAY_DATA 0xBC
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#define F10_NB_ARR_ECC_WR_REQ BIT(17)
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#define SET_NB_DRAM_INJECTION_WRITE(inj) \
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(BIT(((inj.word) & 0xF) + 20) | \
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F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
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#define SET_NB_DRAM_INJECTION_READ(inj) \
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(BIT(((inj.word) & 0xF) + 20) | \
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BIT(16) | inj.bit_map)
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#define NBCAP 0xE8
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#define NBCAP_CHIPKILL BIT(4)
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#define NBCAP_SECDED BIT(3)
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#define NBCAP_DCT_DUAL BIT(0)
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#define EXT_NB_MCA_CFG 0x180
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/* MSRs */
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#define MSR_MCGCTL_NBE BIT(4)
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enum amd_families {
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K8_CPUS = 0,
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F10_CPUS,
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F15_CPUS,
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F15_M30H_CPUS,
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F15_M60H_CPUS,
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F16_CPUS,
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F16_M30H_CPUS,
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NUM_FAMILIES,
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};
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/* Error injection control structure */
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struct error_injection {
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u32 section;
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u32 word;
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u32 bit_map;
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};
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/* low and high part of PCI config space regs */
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struct reg_pair {
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u32 lo, hi;
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};
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/*
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* See F1x[1, 0][7C:40] DRAM Base/Limit Registers
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*/
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struct dram_range {
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struct reg_pair base;
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struct reg_pair lim;
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};
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/* A DCT chip selects collection */
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struct chip_select {
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u32 csbases[NUM_CHIPSELECTS];
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u8 b_cnt;
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u32 csmasks[NUM_CHIPSELECTS];
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u8 m_cnt;
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};
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struct amd64_pvt {
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struct low_ops *ops;
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/* pci_device handles which we utilize */
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struct pci_dev *F1, *F2, *F3;
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u16 mc_node_id; /* MC index of this MC node */
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u8 fam; /* CPU family */
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u8 model; /* ... model */
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u8 stepping; /* ... stepping */
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int ext_model; /* extended model value of this node */
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int channel_count;
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/* Raw registers */
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u32 dclr0; /* DRAM Configuration Low DCT0 reg */
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u32 dclr1; /* DRAM Configuration Low DCT1 reg */
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u32 dchr0; /* DRAM Configuration High DCT0 reg */
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u32 dchr1; /* DRAM Configuration High DCT1 reg */
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u32 nbcap; /* North Bridge Capabilities */
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u32 nbcfg; /* F10 North Bridge Configuration */
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u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */
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u32 dhar; /* DRAM Hoist reg */
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u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
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u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
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/* one for each DCT */
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struct chip_select csels[2];
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/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
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struct dram_range ranges[DRAM_RANGES];
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u64 top_mem; /* top of memory below 4GB */
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u64 top_mem2; /* top of memory above 4GB */
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u32 dct_sel_lo; /* DRAM Controller Select Low */
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u32 dct_sel_hi; /* DRAM Controller Select High */
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u32 online_spare; /* On-Line spare Reg */
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/* x4 or x8 syndromes in use */
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u8 ecc_sym_sz;
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/* place to store error injection parameters prior to issue */
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struct error_injection injection;
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/* cache the dram_type */
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enum mem_type dram_type;
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};
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enum err_codes {
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DECODE_OK = 0,
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ERR_NODE = -1,
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ERR_CSROW = -2,
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ERR_CHANNEL = -3,
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};
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struct err_info {
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int err_code;
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struct mem_ctl_info *src_mci;
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int csrow;
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int channel;
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u16 syndrome;
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u32 page;
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u32 offset;
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};
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static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
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{
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u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
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if (boot_cpu_data.x86 == 0xf)
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return addr;
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return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
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}
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static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
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{
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u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
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if (boot_cpu_data.x86 == 0xf)
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return lim;
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return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
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}
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static inline u16 extract_syndrome(u64 status)
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{
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return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
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}
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static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
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{
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if (pvt->fam == 0x15 && pvt->model >= 0x30)
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return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
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((pvt->dct_sel_lo >> 6) & 0x3);
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return ((pvt)->dct_sel_lo >> 6) & 0x3;
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}
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/*
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* per-node ECC settings descriptor
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*/
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struct ecc_settings {
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u32 old_nbctl;
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bool nbctl_valid;
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struct flags {
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unsigned long nb_mce_enable:1;
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unsigned long nb_ecc_prev:1;
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} flags;
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};
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#ifdef CONFIG_EDAC_DEBUG
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extern const struct attribute_group amd64_edac_dbg_group;
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#endif
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#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
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extern const struct attribute_group amd64_edac_inj_group;
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#endif
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/*
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* Each of the PCI Device IDs types have their own set of hardware accessor
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* functions and per device encoding/decoding logic.
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*/
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struct low_ops {
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int (*early_channel_count) (struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
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struct err_info *);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
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unsigned cs_mode, int cs_mask_nr);
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};
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struct amd64_family_type {
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const char *ctl_name;
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u16 f1_id, f3_id;
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struct low_ops ops;
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};
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int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 *val, const char *func);
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int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 val, const char *func);
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#define amd64_read_pci_cfg(pdev, offset, val) \
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__amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
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#define amd64_write_pci_cfg(pdev, offset, val) \
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__amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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u64 *hole_offset, u64 *hole_size);
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#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
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/* Injection helpers */
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static inline void disable_caches(void *dummy)
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{
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write_cr0(read_cr0() | X86_CR0_CD);
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wbinvd();
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}
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static inline void enable_caches(void *dummy)
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{
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write_cr0(read_cr0() & ~X86_CR0_CD);
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}
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static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
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{
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if (pvt->fam == 0x15 && pvt->model >= 0x30) {
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u32 tmp;
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amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
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return (u8) tmp & 0xF;
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}
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return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
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}
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static inline u8 dhar_valid(struct amd64_pvt *pvt)
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{
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if (pvt->fam == 0x15 && pvt->model >= 0x30) {
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u32 tmp;
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amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
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return (tmp >> 1) & BIT(0);
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}
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return (pvt)->dhar & BIT(0);
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}
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static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
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{
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if (pvt->fam == 0x15 && pvt->model >= 0x30) {
|
|
u32 tmp;
|
|
amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
|
|
return (tmp >> 11) & 0x1FFF;
|
|
}
|
|
return (pvt)->dct_sel_lo & 0xFFFFF800;
|
|
}
|