364 lines
10 KiB
Plaintext
364 lines
10 KiB
Plaintext
#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra124";
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interrupt-parent = <&gic>;
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_TIMER>;
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};
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra124-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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apbdma: dma@60020000 {
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compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
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reg = <0x60020000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
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resets = <&tegra_car 34>;
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reset-names = "dma";
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#dma-cells = <1>;
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};
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pinmux: pinmux@70000868 {
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compatible = "nvidia,tegra124-pinmux";
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reg = <0x70000868 0x164>, /* Pad control registers */
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<0x70003000 0x434>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
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*/
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serial@70006000 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTA>;
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resets = <&tegra_car 6>;
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reset-names = "serial";
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dmas = <&apbdma 8>, <&apbdma 8>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@70006040 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTB>;
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resets = <&tegra_car 7>;
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reset-names = "serial";
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dmas = <&apbdma 9>, <&apbdma 9>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@70006200 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTC>;
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resets = <&tegra_car 55>;
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reset-names = "serial";
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dmas = <&apbdma 10>, <&apbdma 10>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@70006300 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTD>;
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resets = <&tegra_car 65>;
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reset-names = "serial";
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dmas = <&apbdma 19>, <&apbdma 19>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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serial@70006400 {
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compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_UARTE>;
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resets = <&tegra_car 66>;
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reset-names = "serial";
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dmas = <&apbdma 20>, <&apbdma 20>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 21>, <&apbdma 21>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&tegra_car 54>;
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reset-names = "i2c";
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dmas = <&apbdma 22>, <&apbdma 22>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&tegra_car 67>;
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reset-names = "i2c";
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dmas = <&apbdma 23>, <&apbdma 23>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&tegra_car 103>;
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reset-names = "i2c";
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dmas = <&apbdma 26>, <&apbdma 26>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&tegra_car 47>;
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reset-names = "i2c";
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dmas = <&apbdma 24>, <&apbdma 24>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c@7000d100 {
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compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
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reg = <0x7000d100 0x100>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car TEGRA124_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&tegra_car 166>;
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reset-names = "i2c";
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dmas = <&apbdma 30>, <&apbdma 30>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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rtc@7000e000 {
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compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_RTC>;
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};
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pmc@7000e400 {
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compatible = "nvidia,tegra124-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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sdhci@700b0000 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0000 0x200>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
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resets = <&tegra_car 14>;
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reset-names = "sdhci";
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status = "disable";
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};
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sdhci@700b0200 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0200 0x200>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
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resets = <&tegra_car 9>;
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reset-names = "sdhci";
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status = "disable";
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};
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sdhci@700b0400 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0400 0x200>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
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resets = <&tegra_car 69>;
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reset-names = "sdhci";
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status = "disable";
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};
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sdhci@700b0600 {
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compatible = "nvidia,tegra124-sdhci";
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reg = <0x700b0600 0x200>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
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resets = <&tegra_car 15>;
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reset-names = "sdhci";
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status = "disable";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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