464 lines
10 KiB
C
464 lines
10 KiB
C
/*
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* Probe for F81216A LPC to 4 UART
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*
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* Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pnp.h>
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#include <linux/kernel.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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#include "8250.h"
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#define ADDR_PORT 0
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#define DATA_PORT 1
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#define EXIT_KEY 0xAA
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#define CHIP_ID1 0x20
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#define CHIP_ID2 0x21
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#define CHIP_ID_F81865 0x0407
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#define CHIP_ID_F81866 0x1010
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#define CHIP_ID_F81216AD 0x1602
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#define CHIP_ID_F81216H 0x0501
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#define CHIP_ID_F81216 0x0802
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#define VENDOR_ID1 0x23
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#define VENDOR_ID1_VAL 0x19
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#define VENDOR_ID2 0x24
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#define VENDOR_ID2_VAL 0x34
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#define IO_ADDR1 0x61
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#define IO_ADDR2 0x60
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#define LDN 0x7
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#define FINTEK_IRQ_MODE 0x70
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#define IRQ_SHARE BIT(4)
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#define IRQ_MODE_MASK (BIT(6) | BIT(5))
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#define IRQ_LEVEL_LOW 0
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#define IRQ_EDGE_HIGH BIT(5)
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/*
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* F81216H clock source register, the value and mask is the same with F81866,
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* but it's on F0h.
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*
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* Clock speeds for UART (register F0h)
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* 00: 1.8432MHz.
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* 01: 18.432MHz.
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* 10: 24MHz.
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* 11: 14.769MHz.
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*/
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#define RS485 0xF0
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#define RTS_INVERT BIT(5)
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#define RS485_URA BIT(4)
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#define RXW4C_IRA BIT(3)
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#define TXW4C_IRA BIT(2)
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#define FIFO_CTRL 0xF6
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#define FIFO_MODE_MASK (BIT(1) | BIT(0))
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#define FIFO_MODE_128 (BIT(1) | BIT(0))
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#define RXFTHR_MODE_MASK (BIT(5) | BIT(4))
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#define RXFTHR_MODE_4X BIT(5)
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#define F81216_LDN_LOW 0x0
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#define F81216_LDN_HIGH 0x4
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/*
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* F81866 registers
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*
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* The IRQ setting mode of F81866 is not the same with F81216 series.
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* Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
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* Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
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*
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* Clock speeds for UART (register F2h)
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* 00: 1.8432MHz.
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* 01: 18.432MHz.
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* 10: 24MHz.
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* 11: 14.769MHz.
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*/
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#define F81866_IRQ_MODE 0xf0
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#define F81866_IRQ_SHARE BIT(0)
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#define F81866_IRQ_MODE0 BIT(1)
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#define F81866_FIFO_CTRL FIFO_CTRL
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#define F81866_IRQ_MODE1 BIT(3)
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#define F81866_LDN_LOW 0x10
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#define F81866_LDN_HIGH 0x16
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#define F81866_UART_CLK 0xF2
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#define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
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#define F81866_UART_CLK_1_8432MHZ 0
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#define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
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#define F81866_UART_CLK_18_432MHZ BIT(0)
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#define F81866_UART_CLK_24MHZ BIT(1)
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struct fintek_8250 {
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u16 pid;
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u16 base_port;
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u8 index;
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u8 key;
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};
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static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
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{
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outb(reg, pdata->base_port + ADDR_PORT);
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return inb(pdata->base_port + DATA_PORT);
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}
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static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
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{
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outb(reg, pdata->base_port + ADDR_PORT);
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outb(data, pdata->base_port + DATA_PORT);
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}
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static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
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u8 data)
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{
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u8 tmp;
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tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
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sio_write_reg(pdata, reg, tmp);
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}
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static int fintek_8250_enter_key(u16 base_port, u8 key)
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{
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if (!request_muxed_region(base_port, 2, "8250_fintek"))
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return -EBUSY;
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/* Force to deactive all SuperIO in this base_port */
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outb(EXIT_KEY, base_port + ADDR_PORT);
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outb(key, base_port + ADDR_PORT);
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outb(key, base_port + ADDR_PORT);
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return 0;
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}
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static void fintek_8250_exit_key(u16 base_port)
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{
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outb(EXIT_KEY, base_port + ADDR_PORT);
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release_region(base_port + ADDR_PORT, 2);
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}
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static int fintek_8250_check_id(struct fintek_8250 *pdata)
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{
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u16 chip;
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if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
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return -ENODEV;
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if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
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return -ENODEV;
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chip = sio_read_reg(pdata, CHIP_ID1);
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chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
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switch (chip) {
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case CHIP_ID_F81865:
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case CHIP_ID_F81866:
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case CHIP_ID_F81216AD:
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case CHIP_ID_F81216H:
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case CHIP_ID_F81216:
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break;
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default:
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return -ENODEV;
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}
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pdata->pid = chip;
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return 0;
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}
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static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
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int *max)
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{
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switch (pdata->pid) {
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case CHIP_ID_F81865:
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case CHIP_ID_F81866:
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*min = F81866_LDN_LOW;
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*max = F81866_LDN_HIGH;
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return 0;
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case CHIP_ID_F81216AD:
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case CHIP_ID_F81216H:
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case CHIP_ID_F81216:
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*min = F81216_LDN_LOW;
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*max = F81216_LDN_HIGH;
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return 0;
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}
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return -ENODEV;
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}
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static int fintek_8250_rs485_config(struct uart_port *port,
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struct serial_rs485 *rs485)
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{
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uint8_t config = 0;
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struct fintek_8250 *pdata = port->private_data;
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if (!pdata)
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return -EINVAL;
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if (rs485->flags & SER_RS485_ENABLED)
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memset(rs485->padding, 0, sizeof(rs485->padding));
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else
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memset(rs485, 0, sizeof(*rs485));
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rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
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SER_RS485_RTS_AFTER_SEND;
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if (rs485->delay_rts_before_send) {
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rs485->delay_rts_before_send = 1;
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config |= TXW4C_IRA;
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}
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if (rs485->delay_rts_after_send) {
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rs485->delay_rts_after_send = 1;
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config |= RXW4C_IRA;
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}
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if ((!!(rs485->flags & SER_RS485_RTS_ON_SEND)) ==
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(!!(rs485->flags & SER_RS485_RTS_AFTER_SEND)))
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rs485->flags &= ~SER_RS485_ENABLED;
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else
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config |= RS485_URA;
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if (rs485->flags & SER_RS485_RTS_ON_SEND)
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config |= RTS_INVERT;
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if (fintek_8250_enter_key(pdata->base_port, pdata->key))
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return -EBUSY;
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sio_write_reg(pdata, LDN, pdata->index);
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sio_write_reg(pdata, RS485, config);
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fintek_8250_exit_key(pdata->base_port);
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port->rs485 = *rs485;
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return 0;
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}
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static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
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{
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sio_write_reg(pdata, LDN, pdata->index);
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switch (pdata->pid) {
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case CHIP_ID_F81866:
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sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
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0);
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/* fall through */
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case CHIP_ID_F81865:
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sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
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F81866_IRQ_SHARE);
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sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
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is_level ? 0 : F81866_IRQ_MODE0);
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break;
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case CHIP_ID_F81216AD:
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case CHIP_ID_F81216H:
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case CHIP_ID_F81216:
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sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
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IRQ_SHARE);
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sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
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is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
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break;
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}
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}
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static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
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{
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switch (pdata->pid) {
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case CHIP_ID_F81216H: /* 128Bytes FIFO */
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case CHIP_ID_F81866:
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sio_write_mask_reg(pdata, FIFO_CTRL,
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FIFO_MODE_MASK | RXFTHR_MODE_MASK,
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FIFO_MODE_128 | RXFTHR_MODE_4X);
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break;
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default: /* Default 16Bytes FIFO */
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break;
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}
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}
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static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
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struct fintek_8250 *pdata)
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{
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sio_write_reg(pdata, LDN, pdata->index);
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switch (pdata->pid) {
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case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
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sio_write_mask_reg(pdata, F81866_UART_CLK,
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F81866_UART_CLK_MASK,
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F81866_UART_CLK_14_769MHZ);
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uart->port.uartclk = 921600 * 16;
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break;
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default: /* leave clock speed untouched */
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break;
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}
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}
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void fintek_8250_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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struct fintek_8250 *pdata = port->private_data;
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unsigned int baud = tty_termios_baud_rate(termios);
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int i;
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u8 reg;
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static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
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static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
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F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
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F81866_UART_CLK_24MHZ };
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switch (pdata->pid) {
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case CHIP_ID_F81216H:
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reg = RS485;
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break;
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case CHIP_ID_F81866:
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reg = F81866_UART_CLK;
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break;
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default:
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/* Don't change clocksource with unknown PID */
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dev_warn(port->dev,
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"%s: pid: %x Not support. use default set_termios.\n",
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__func__, pdata->pid);
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serial8250_do_set_termios(port, termios, old);
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return;
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}
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for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
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if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
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continue;
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if (port->uartclk == baudrate_table[i] * 16)
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break;
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if (fintek_8250_enter_key(pdata->base_port, pdata->key))
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continue;
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port->uartclk = baudrate_table[i] * 16;
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sio_write_reg(pdata, LDN, pdata->index);
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sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
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clock_table[i]);
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fintek_8250_exit_key(pdata->base_port);
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break;
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}
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if (i == ARRAY_SIZE(baudrate_table)) {
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baud = tty_termios_baud_rate(old);
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tty_termios_encode_baud_rate(termios, baud, baud);
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}
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serial8250_do_set_termios(port, termios, old);
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}
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static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
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{
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struct fintek_8250 *pdata = uart->port.private_data;
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switch (pdata->pid) {
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case CHIP_ID_F81216H:
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case CHIP_ID_F81866:
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uart->port.set_termios = fintek_8250_set_termios;
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break;
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default:
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break;
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}
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}
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static int probe_setup_port(struct fintek_8250 *pdata,
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struct uart_8250_port *uart)
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{
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static const u16 addr[] = {0x4e, 0x2e};
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static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
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struct irq_data *irq_data;
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bool level_mode = false;
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int i, j, k, min, max;
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for (i = 0; i < ARRAY_SIZE(addr); i++) {
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for (j = 0; j < ARRAY_SIZE(keys); j++) {
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pdata->base_port = addr[i];
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pdata->key = keys[j];
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if (fintek_8250_enter_key(addr[i], keys[j]))
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continue;
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if (fintek_8250_check_id(pdata) ||
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fintek_8250_get_ldn_range(pdata, &min, &max)) {
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fintek_8250_exit_key(addr[i]);
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continue;
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}
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for (k = min; k < max; k++) {
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u16 aux;
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sio_write_reg(pdata, LDN, k);
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aux = sio_read_reg(pdata, IO_ADDR1);
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aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
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if (aux != uart->port.iobase)
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continue;
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pdata->index = k;
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irq_data = irq_get_irq_data(uart->port.irq);
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if (irq_data)
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level_mode =
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irqd_is_level_type(irq_data);
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fintek_8250_set_irq_mode(pdata, level_mode);
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fintek_8250_set_max_fifo(pdata);
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fintek_8250_goto_highspeed(uart, pdata);
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fintek_8250_exit_key(addr[i]);
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return 0;
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}
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fintek_8250_exit_key(addr[i]);
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}
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}
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return -ENODEV;
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}
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static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
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{
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struct fintek_8250 *pdata = uart->port.private_data;
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switch (pdata->pid) {
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case CHIP_ID_F81216AD:
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case CHIP_ID_F81216H:
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case CHIP_ID_F81866:
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case CHIP_ID_F81865:
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uart->port.rs485_config = fintek_8250_rs485_config;
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break;
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default: /* No RS485 Auto direction functional */
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break;
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}
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}
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int fintek_8250_probe(struct uart_8250_port *uart)
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{
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struct fintek_8250 *pdata;
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struct fintek_8250 probe_data;
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if (probe_setup_port(&probe_data, uart))
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return -ENODEV;
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pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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memcpy(pdata, &probe_data, sizeof(probe_data));
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uart->port.private_data = pdata;
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fintek_8250_set_rs485_handler(uart);
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fintek_8250_set_termios_handler(uart);
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return 0;
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}
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