263 lines
7.7 KiB
C
263 lines
7.7 KiB
C
/* Copyright (c) 2009 - 2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "bman_priv.h"
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u16 bman_ip_rev;
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EXPORT_SYMBOL(bman_ip_rev);
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/* Register offsets */
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#define REG_FBPR_FPC 0x0800
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#define REG_ECSR 0x0a00
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#define REG_ECIR 0x0a04
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#define REG_EADR 0x0a08
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#define REG_EDATA(n) (0x0a10 + ((n) * 0x04))
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#define REG_SBEC(n) (0x0a80 + ((n) * 0x04))
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#define REG_IP_REV_1 0x0bf8
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#define REG_IP_REV_2 0x0bfc
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#define REG_FBPR_BARE 0x0c00
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#define REG_FBPR_BAR 0x0c04
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#define REG_FBPR_AR 0x0c10
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#define REG_SRCIDR 0x0d04
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#define REG_LIODNR 0x0d08
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#define REG_ERR_ISR 0x0e00
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#define REG_ERR_IER 0x0e04
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#define REG_ERR_ISDR 0x0e08
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/* Used by all error interrupt registers except 'inhibit' */
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#define BM_EIRQ_IVCI 0x00000010 /* Invalid Command Verb */
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#define BM_EIRQ_FLWI 0x00000008 /* FBPR Low Watermark */
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#define BM_EIRQ_MBEI 0x00000004 /* Multi-bit ECC Error */
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#define BM_EIRQ_SBEI 0x00000002 /* Single-bit ECC Error */
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#define BM_EIRQ_BSCN 0x00000001 /* pool State Change Notification */
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struct bman_hwerr_txt {
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u32 mask;
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const char *txt;
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};
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static const struct bman_hwerr_txt bman_hwerr_txts[] = {
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{ BM_EIRQ_IVCI, "Invalid Command Verb" },
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{ BM_EIRQ_FLWI, "FBPR Low Watermark" },
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{ BM_EIRQ_MBEI, "Multi-bit ECC Error" },
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{ BM_EIRQ_SBEI, "Single-bit ECC Error" },
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{ BM_EIRQ_BSCN, "Pool State Change Notification" },
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};
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/* Only trigger low water mark interrupt once only */
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#define BMAN_ERRS_TO_DISABLE BM_EIRQ_FLWI
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/* Pointer to the start of the BMan's CCSR space */
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static u32 __iomem *bm_ccsr_start;
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static inline u32 bm_ccsr_in(u32 offset)
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{
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return ioread32be(bm_ccsr_start + offset/4);
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}
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static inline void bm_ccsr_out(u32 offset, u32 val)
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{
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iowrite32be(val, bm_ccsr_start + offset/4);
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}
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static void bm_get_version(u16 *id, u8 *major, u8 *minor)
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{
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u32 v = bm_ccsr_in(REG_IP_REV_1);
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*id = (v >> 16);
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*major = (v >> 8) & 0xff;
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*minor = v & 0xff;
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}
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/* signal transactions for FBPRs with higher priority */
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#define FBPR_AR_RPRIO_HI BIT(30)
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static void bm_set_memory(u64 ba, u32 size)
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{
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u32 exp = ilog2(size);
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/* choke if size isn't within range */
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DPAA_ASSERT(size >= 4096 && size <= 1024*1024*1024 &&
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is_power_of_2(size));
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/* choke if '[e]ba' has lower-alignment than 'size' */
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DPAA_ASSERT(!(ba & (size - 1)));
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bm_ccsr_out(REG_FBPR_BARE, upper_32_bits(ba));
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bm_ccsr_out(REG_FBPR_BAR, lower_32_bits(ba));
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bm_ccsr_out(REG_FBPR_AR, exp - 1);
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}
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/*
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* Location and size of BMan private memory
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*
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* Ideally we would use the DMA API to turn rmem->base into a DMA address
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* (especially if iommu translations ever get involved). Unfortunately, the
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* DMA API currently does not allow mapping anything that is not backed with
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* a struct page.
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*/
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static dma_addr_t fbpr_a;
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static size_t fbpr_sz;
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static int bman_fbpr(struct reserved_mem *rmem)
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{
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fbpr_a = rmem->base;
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fbpr_sz = rmem->size;
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WARN_ON(!(fbpr_a && fbpr_sz));
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return 0;
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}
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RESERVEDMEM_OF_DECLARE(bman_fbpr, "fsl,bman-fbpr", bman_fbpr);
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static irqreturn_t bman_isr(int irq, void *ptr)
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{
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u32 isr_val, ier_val, ecsr_val, isr_mask, i;
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struct device *dev = ptr;
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ier_val = bm_ccsr_in(REG_ERR_IER);
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isr_val = bm_ccsr_in(REG_ERR_ISR);
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ecsr_val = bm_ccsr_in(REG_ECSR);
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isr_mask = isr_val & ier_val;
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if (!isr_mask)
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return IRQ_NONE;
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for (i = 0; i < ARRAY_SIZE(bman_hwerr_txts); i++) {
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if (bman_hwerr_txts[i].mask & isr_mask) {
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dev_err_ratelimited(dev, "ErrInt: %s\n",
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bman_hwerr_txts[i].txt);
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if (bman_hwerr_txts[i].mask & ecsr_val) {
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/* Re-arm error capture registers */
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bm_ccsr_out(REG_ECSR, ecsr_val);
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}
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if (bman_hwerr_txts[i].mask & BMAN_ERRS_TO_DISABLE) {
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dev_dbg(dev, "Disabling error 0x%x\n",
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bman_hwerr_txts[i].mask);
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ier_val &= ~bman_hwerr_txts[i].mask;
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bm_ccsr_out(REG_ERR_IER, ier_val);
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}
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}
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}
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bm_ccsr_out(REG_ERR_ISR, isr_val);
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return IRQ_HANDLED;
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}
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static int fsl_bman_probe(struct platform_device *pdev)
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{
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int ret, err_irq;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct resource *res;
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u16 id, bm_pool_cnt;
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u8 major, minor;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "Can't get %s property 'IORESOURCE_MEM'\n",
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node->full_name);
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return -ENXIO;
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}
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bm_ccsr_start = devm_ioremap(dev, res->start, resource_size(res));
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if (!bm_ccsr_start)
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return -ENXIO;
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bm_get_version(&id, &major, &minor);
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if (major == 1 && minor == 0) {
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bman_ip_rev = BMAN_REV10;
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bm_pool_cnt = BM_POOL_MAX;
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} else if (major == 2 && minor == 0) {
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bman_ip_rev = BMAN_REV20;
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bm_pool_cnt = 8;
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} else if (major == 2 && minor == 1) {
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bman_ip_rev = BMAN_REV21;
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bm_pool_cnt = BM_POOL_MAX;
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} else {
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dev_err(dev, "Unknown Bman version:%04x,%02x,%02x\n",
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id, major, minor);
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return -ENODEV;
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}
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bm_set_memory(fbpr_a, fbpr_sz);
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err_irq = platform_get_irq(pdev, 0);
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if (err_irq <= 0) {
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dev_info(dev, "Can't get %s IRQ\n", node->full_name);
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return -ENODEV;
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}
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ret = devm_request_irq(dev, err_irq, bman_isr, IRQF_SHARED, "bman-err",
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dev);
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if (ret) {
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dev_err(dev, "devm_request_irq() failed %d for '%s'\n",
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ret, node->full_name);
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return ret;
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}
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/* Disable Buffer Pool State Change */
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bm_ccsr_out(REG_ERR_ISDR, BM_EIRQ_BSCN);
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/*
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* Write-to-clear any stale bits, (eg. starvation being asserted prior
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* to resource allocation during driver init).
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*/
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bm_ccsr_out(REG_ERR_ISR, 0xffffffff);
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/* Enable Error Interrupts */
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bm_ccsr_out(REG_ERR_IER, 0xffffffff);
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bm_bpalloc = devm_gen_pool_create(dev, 0, -1, "bman-bpalloc");
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if (IS_ERR(bm_bpalloc)) {
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ret = PTR_ERR(bm_bpalloc);
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dev_err(dev, "bman-bpalloc pool init failed (%d)\n", ret);
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return ret;
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}
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/* seed BMan resource pool */
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ret = gen_pool_add(bm_bpalloc, DPAA_GENALLOC_OFF, bm_pool_cnt, -1);
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if (ret) {
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dev_err(dev, "Failed to seed BPID range [%d..%d] (%d)\n",
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0, bm_pool_cnt - 1, ret);
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return ret;
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}
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return 0;
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};
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static const struct of_device_id fsl_bman_ids[] = {
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{
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.compatible = "fsl,bman",
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},
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{}
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};
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static struct platform_driver fsl_bman_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = fsl_bman_ids,
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.suppress_bind_attrs = true,
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},
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.probe = fsl_bman_probe,
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};
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builtin_platform_driver(fsl_bman_driver);
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