135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/*
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* Copyright (c) 2016 Hisilicon Limited.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _HNS_ROCE_EQ_H
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#define _HNS_ROCE_EQ_H
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#define HNS_ROCE_CEQ 1
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#define HNS_ROCE_AEQ 2
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#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
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#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
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#define HNS_ROCE_CEQC_REG_OFFSET 0x18
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#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
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#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
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#define HNS_ROCE_INT_MASK_DISABLE 0
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#define HNS_ROCE_INT_MASK_ENABLE 1
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#define EQ_ENABLE 1
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#define EQ_DISABLE 0
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#define CONS_INDEX_MASK 0xffff
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#define CEQ_REG_OFFSET 0x18
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enum {
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HNS_ROCE_EQ_STAT_INVALID = 0,
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HNS_ROCE_EQ_STAT_VALID = 2,
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};
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struct hns_roce_aeqe {
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u32 asyn;
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union {
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struct {
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u32 qp;
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u32 rsv0;
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u32 rsv1;
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} qp_event;
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struct {
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u32 cq;
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u32 rsv0;
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u32 rsv1;
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} cq_event;
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struct {
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u32 port;
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u32 rsv0;
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u32 rsv1;
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} port_event;
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struct {
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u32 ceqe;
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u32 rsv0;
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u32 rsv1;
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} ce_event;
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struct {
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__le64 out_param;
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__le16 token;
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u8 status;
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u8 rsv0;
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} __packed cmd;
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} event;
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};
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#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
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#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M \
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(((1UL << 8) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S)
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#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
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#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M \
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(((1UL << 7) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)
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#define HNS_ROCE_AEQE_U32_4_OWNER_S 31
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#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
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#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M \
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(((1UL << 24) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S)
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#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
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#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M \
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(((1UL << 3) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S)
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#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
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#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M \
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(((1UL << 16) - 1) << HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S)
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#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
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#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M \
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(((1UL << 5) - 1) << HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S)
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struct hns_roce_ceqe {
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union {
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int comp;
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} ceqe;
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};
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#define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
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#define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
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#define HNS_ROCE_CEQE_CEQE_COMP_CQN_M \
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(((1UL << 16) - 1) << HNS_ROCE_CEQE_CEQE_COMP_CQN_S)
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#endif /* _HNS_ROCE_EQ_H */
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