365 lines
8.6 KiB
C
365 lines
8.6 KiB
C
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/bcma/bcma.h>
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#include <linux/spi/spi.h>
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#include "spi-bcm53xx.h"
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#define BCM53XXSPI_MAX_SPI_BAUD 13500000 /* 216 MHz? */
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#define BCM53XXSPI_FLASH_WINDOW SZ_32M
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/* The longest observed required wait was 19 ms */
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#define BCM53XXSPI_SPE_TIMEOUT_MS 80
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struct bcm53xxspi {
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struct bcma_device *core;
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struct spi_master *master;
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void __iomem *mmio_base;
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size_t read_offset;
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bool bspi; /* Boot SPI mode with memory mapping */
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};
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static inline u32 bcm53xxspi_read(struct bcm53xxspi *b53spi, u16 offset)
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{
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return bcma_read32(b53spi->core, offset);
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}
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static inline void bcm53xxspi_write(struct bcm53xxspi *b53spi, u16 offset,
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u32 value)
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{
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bcma_write32(b53spi->core, offset, value);
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}
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static void bcm53xxspi_disable_bspi(struct bcm53xxspi *b53spi)
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{
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struct device *dev = &b53spi->core->dev;
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unsigned long deadline;
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u32 tmp;
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if (!b53spi->bspi)
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return;
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tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
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if (tmp & 0x1)
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return;
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deadline = jiffies + usecs_to_jiffies(200);
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do {
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tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_BUSY_STATUS);
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if (!(tmp & 0x1)) {
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bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL,
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0x1);
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ndelay(200);
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b53spi->bspi = false;
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return;
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}
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udelay(1);
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} while (!time_after_eq(jiffies, deadline));
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dev_warn(dev, "Timeout disabling BSPI\n");
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}
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static void bcm53xxspi_enable_bspi(struct bcm53xxspi *b53spi)
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{
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u32 tmp;
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if (b53spi->bspi)
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return;
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tmp = bcm53xxspi_read(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL);
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if (!(tmp & 0x1))
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return;
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bcm53xxspi_write(b53spi, B53SPI_BSPI_MAST_N_BOOT_CTRL, 0x0);
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b53spi->bspi = true;
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}
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static inline unsigned int bcm53xxspi_calc_timeout(size_t len)
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{
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/* Do some magic calculation based on length and buad. Add 10% and 1. */
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return (len * 9000 / BCM53XXSPI_MAX_SPI_BAUD * 110 / 100) + 1;
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}
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static int bcm53xxspi_wait(struct bcm53xxspi *b53spi, unsigned int timeout_ms)
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{
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unsigned long deadline;
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u32 tmp;
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/* SPE bit has to be 0 before we read MSPI STATUS */
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deadline = jiffies + msecs_to_jiffies(BCM53XXSPI_SPE_TIMEOUT_MS);
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do {
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tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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if (!(tmp & B53SPI_MSPI_SPCR2_SPE))
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break;
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udelay(5);
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} while (!time_after_eq(jiffies, deadline));
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if (tmp & B53SPI_MSPI_SPCR2_SPE)
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goto spi_timeout;
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/* Check status */
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deadline = jiffies + msecs_to_jiffies(timeout_ms);
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do {
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tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_MSPI_STATUS);
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if (tmp & B53SPI_MSPI_MSPI_STATUS_SPIF) {
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bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
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return 0;
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}
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cpu_relax();
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udelay(100);
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} while (!time_after_eq(jiffies, deadline));
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spi_timeout:
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bcm53xxspi_write(b53spi, B53SPI_MSPI_MSPI_STATUS, 0);
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pr_err("Timeout waiting for SPI to be ready!\n");
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return -EBUSY;
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}
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static void bcm53xxspi_buf_write(struct bcm53xxspi *b53spi, u8 *w_buf,
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size_t len, bool cont)
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{
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u32 tmp;
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int i;
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for (i = 0; i < len; i++) {
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/* Transmit Register File MSB */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_TXRAM + 4 * (i * 2),
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(unsigned int)w_buf[i]);
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}
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for (i = 0; i < len; i++) {
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tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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B53SPI_CDRAM_PCS_DSCK;
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if (!cont && i == len - 1)
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tmp &= ~B53SPI_CDRAM_CONT;
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tmp &= ~0x1;
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/* Command Register File */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
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}
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/* Set queue pointers */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP, len - 1);
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if (cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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/* Start SPI transfer */
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tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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tmp |= B53SPI_MSPI_SPCR2_SPE;
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if (cont)
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tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
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bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
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/* Wait for SPI to finish */
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bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
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if (!cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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b53spi->read_offset = len;
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}
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static void bcm53xxspi_buf_read(struct bcm53xxspi *b53spi, u8 *r_buf,
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size_t len, bool cont)
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{
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u32 tmp;
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int i;
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for (i = 0; i < b53spi->read_offset + len; i++) {
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tmp = B53SPI_CDRAM_CONT | B53SPI_CDRAM_PCS_DISABLE_ALL |
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B53SPI_CDRAM_PCS_DSCK;
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if (!cont && i == b53spi->read_offset + len - 1)
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tmp &= ~B53SPI_CDRAM_CONT;
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tmp &= ~0x1;
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/* Command Register File */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_CDRAM + 4 * i, tmp);
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}
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/* Set queue pointers */
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bcm53xxspi_write(b53spi, B53SPI_MSPI_NEWQP, 0);
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bcm53xxspi_write(b53spi, B53SPI_MSPI_ENDQP,
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b53spi->read_offset + len - 1);
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if (cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 1);
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/* Start SPI transfer */
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tmp = bcm53xxspi_read(b53spi, B53SPI_MSPI_SPCR2);
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tmp |= B53SPI_MSPI_SPCR2_SPE;
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if (cont)
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tmp |= B53SPI_MSPI_SPCR2_CONT_AFTER_CMD;
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bcm53xxspi_write(b53spi, B53SPI_MSPI_SPCR2, tmp);
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/* Wait for SPI to finish */
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bcm53xxspi_wait(b53spi, bcm53xxspi_calc_timeout(len));
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if (!cont)
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bcm53xxspi_write(b53spi, B53SPI_MSPI_WRITE_LOCK, 0);
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for (i = 0; i < len; ++i) {
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int offset = b53spi->read_offset + i;
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/* Data stored in the transmit register file LSB */
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r_buf[i] = (u8)bcm53xxspi_read(b53spi, B53SPI_MSPI_RXRAM + 4 * (1 + offset * 2));
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}
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b53spi->read_offset = 0;
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}
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static int bcm53xxspi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct bcm53xxspi *b53spi = spi_master_get_devdata(master);
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u8 *buf;
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size_t left;
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bcm53xxspi_disable_bspi(b53spi);
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if (t->tx_buf) {
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buf = (u8 *)t->tx_buf;
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left = t->len;
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while (left) {
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size_t to_write = min_t(size_t, 16, left);
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bool cont = left - to_write > 0;
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bcm53xxspi_buf_write(b53spi, buf, to_write, cont);
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left -= to_write;
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buf += to_write;
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}
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}
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if (t->rx_buf) {
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buf = (u8 *)t->rx_buf;
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left = t->len;
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while (left) {
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size_t to_read = min_t(size_t, 16 - b53spi->read_offset,
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left);
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bool cont = left - to_read > 0;
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bcm53xxspi_buf_read(b53spi, buf, to_read, cont);
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left -= to_read;
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buf += to_read;
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}
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}
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return 0;
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}
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static int bcm53xxspi_flash_read(struct spi_device *spi,
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struct spi_flash_read_message *msg)
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{
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struct bcm53xxspi *b53spi = spi_master_get_devdata(spi->master);
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int ret = 0;
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if (msg->from + msg->len > BCM53XXSPI_FLASH_WINDOW)
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return -EINVAL;
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bcm53xxspi_enable_bspi(b53spi);
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memcpy_fromio(msg->buf, b53spi->mmio_base + msg->from, msg->len);
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msg->retlen = msg->len;
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return ret;
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}
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/**************************************************
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* BCMA
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**************************************************/
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static struct spi_board_info bcm53xx_info = {
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.modalias = "bcm53xxspiflash",
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};
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static const struct bcma_device_id bcm53xxspi_bcma_tbl[] = {
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BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_QSPI, BCMA_ANY_REV, BCMA_ANY_CLASS),
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{},
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};
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MODULE_DEVICE_TABLE(bcma, bcm53xxspi_bcma_tbl);
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static int bcm53xxspi_bcma_probe(struct bcma_device *core)
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{
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struct device *dev = &core->dev;
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struct bcm53xxspi *b53spi;
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struct spi_master *master;
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int err;
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if (core->bus->drv_cc.core->id.rev != 42) {
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pr_err("SPI on SoC with unsupported ChipCommon rev\n");
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return -ENOTSUPP;
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}
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master = spi_alloc_master(dev, sizeof(*b53spi));
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if (!master)
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return -ENOMEM;
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b53spi = spi_master_get_devdata(master);
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b53spi->master = master;
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b53spi->core = core;
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if (core->addr_s[0])
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b53spi->mmio_base = devm_ioremap(dev, core->addr_s[0],
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BCM53XXSPI_FLASH_WINDOW);
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b53spi->bspi = true;
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bcm53xxspi_disable_bspi(b53spi);
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master->transfer_one = bcm53xxspi_transfer_one;
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if (b53spi->mmio_base)
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master->spi_flash_read = bcm53xxspi_flash_read;
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bcma_set_drvdata(core, b53spi);
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err = devm_spi_register_master(dev, master);
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if (err) {
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spi_master_put(master);
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bcma_set_drvdata(core, NULL);
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return err;
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}
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/* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */
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spi_new_device(master, &bcm53xx_info);
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return 0;
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}
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static struct bcma_driver bcm53xxspi_bcma_driver = {
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.name = KBUILD_MODNAME,
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.id_table = bcm53xxspi_bcma_tbl,
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.probe = bcm53xxspi_bcma_probe,
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};
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/**************************************************
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* Init & exit
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**************************************************/
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static int __init bcm53xxspi_module_init(void)
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{
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int err = 0;
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err = bcma_driver_register(&bcm53xxspi_bcma_driver);
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if (err)
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pr_err("Failed to register bcma driver: %d\n", err);
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return err;
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}
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static void __exit bcm53xxspi_module_exit(void)
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{
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bcma_driver_unregister(&bcm53xxspi_bcma_driver);
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}
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module_init(bcm53xxspi_module_init);
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module_exit(bcm53xxspi_module_exit);
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MODULE_DESCRIPTION("Broadcom BCM53xx SPI Controller driver");
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MODULE_AUTHOR("Rafał Miłecki <zajec5@gmail.com>");
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MODULE_LICENSE("GPL");
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