331 lines
8.4 KiB
C
331 lines
8.4 KiB
C
/*
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* SMP support for power macintosh.
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*
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* We support both the old "powersurge" SMP architecture
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* and the current Core99 (G4 PowerMac) machines.
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*
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* Note that we don't support the very first rev. of
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* Apple/DayStar 2 CPUs board, the one with the funky
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* watchdog. Hopefully, none of these should be there except
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* maybe internally to Apple. I should probably still add some
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* code to detect this card though and disable SMP. --BenH.
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*
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* Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
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* and Ben Herrenschmidt <benh@kernel.crashing.org>.
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*
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* Support for DayStar quad CPU cards
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* Copyright (C) XLR8, Inc. 1994-2000
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/irq.h>
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#include <asm/ptrace.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/time.h>
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#include <asm/cacheflush.h>
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#include <asm/keylargo.h>
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#include <asm/pmac_low_i2c.h>
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#include "mpic.h"
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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extern void pmac_secondary_start_1(void);
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extern void pmac_secondary_start_2(void);
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extern void pmac_secondary_start_3(void);
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extern struct smp_ops_t *smp_ops;
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static void (*pmac_tb_freeze)(int freeze);
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static struct device_node *pmac_tb_clock_chip_host;
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static u8 pmac_tb_pulsar_addr;
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static DEFINE_SPINLOCK(timebase_lock);
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static unsigned long timebase;
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static void smp_core99_cypress_tb_freeze(int freeze)
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{
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u8 data;
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int rc;
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/* Strangely, the device-tree says address is 0xd2, but darwin
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* accesses 0xd0 ...
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*/
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pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
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rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
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0xd0 | pmac_low_i2c_read,
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0x81, &data, 1);
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if (rc != 0)
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goto bail;
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data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
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pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
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rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
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0xd0 | pmac_low_i2c_write,
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0x81, &data, 1);
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bail:
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if (rc != 0) {
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printk("Cypress Timebase %s rc: %d\n",
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freeze ? "freeze" : "unfreeze", rc);
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panic("Timebase freeze failed !\n");
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}
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}
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static void smp_core99_pulsar_tb_freeze(int freeze)
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{
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u8 data;
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int rc;
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pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_combined);
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rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
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pmac_tb_pulsar_addr | pmac_low_i2c_read,
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0x2e, &data, 1);
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if (rc != 0)
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goto bail;
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data = (data & 0x88) | (freeze ? 0x11 : 0x22);
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pmac_low_i2c_setmode(pmac_tb_clock_chip_host, pmac_low_i2c_mode_stdsub);
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rc = pmac_low_i2c_xfer(pmac_tb_clock_chip_host,
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pmac_tb_pulsar_addr | pmac_low_i2c_write,
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0x2e, &data, 1);
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bail:
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if (rc != 0) {
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printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
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freeze ? "freeze" : "unfreeze", rc);
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panic("Timebase freeze failed !\n");
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}
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}
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static void smp_core99_give_timebase(void)
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{
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/* Open i2c bus for synchronous access */
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if (pmac_low_i2c_open(pmac_tb_clock_chip_host, 0))
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panic("Can't open i2c for TB sync !\n");
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spin_lock(&timebase_lock);
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(*pmac_tb_freeze)(1);
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mb();
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timebase = get_tb();
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spin_unlock(&timebase_lock);
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while (timebase)
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barrier();
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spin_lock(&timebase_lock);
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(*pmac_tb_freeze)(0);
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spin_unlock(&timebase_lock);
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/* Close i2c bus */
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pmac_low_i2c_close(pmac_tb_clock_chip_host);
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}
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static void __devinit smp_core99_take_timebase(void)
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{
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while (!timebase)
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barrier();
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spin_lock(&timebase_lock);
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set_tb(timebase >> 32, timebase & 0xffffffff);
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timebase = 0;
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spin_unlock(&timebase_lock);
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}
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static int __init smp_core99_probe(void)
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{
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struct device_node *cpus;
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struct device_node *cc;
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int ncpus = 0;
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/* Maybe use systemconfiguration here ? */
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if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
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/* Count CPUs in the device-tree */
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for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;)
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++ncpus;
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printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
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/* Nothing more to do if less than 2 of them */
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if (ncpus <= 1)
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return 1;
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/* HW sync only on these platforms */
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if (!machine_is_compatible("PowerMac7,2") &&
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!machine_is_compatible("PowerMac7,3") &&
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!machine_is_compatible("RackMac3,1"))
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goto nohwsync;
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/* Look for the clock chip */
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for (cc = NULL; (cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL;) {
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struct device_node *p = of_get_parent(cc);
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u32 *reg;
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int ok;
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ok = p && device_is_compatible(p, "uni-n-i2c");
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if (!ok)
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goto next;
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reg = (u32 *)get_property(cc, "reg", NULL);
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if (reg == NULL)
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goto next;
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switch (*reg) {
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case 0xd2:
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if (device_is_compatible(cc, "pulsar-legacy-slewing")) {
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pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
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pmac_tb_pulsar_addr = 0xd2;
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printk(KERN_INFO "Timebase clock is Pulsar chip\n");
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} else if (device_is_compatible(cc, "cy28508")) {
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pmac_tb_freeze = smp_core99_cypress_tb_freeze;
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printk(KERN_INFO "Timebase clock is Cypress chip\n");
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}
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break;
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case 0xd4:
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pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
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pmac_tb_pulsar_addr = 0xd4;
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printk(KERN_INFO "Timebase clock is Pulsar chip\n");
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break;
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}
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if (pmac_tb_freeze != NULL) {
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pmac_tb_clock_chip_host = p;
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smp_ops->give_timebase = smp_core99_give_timebase;
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smp_ops->take_timebase = smp_core99_take_timebase;
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of_node_put(cc);
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of_node_put(p);
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break;
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}
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next:
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of_node_put(p);
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}
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nohwsync:
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mpic_request_ipis();
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return ncpus;
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}
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static void __init smp_core99_kick_cpu(int nr)
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{
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int save_vector, j;
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unsigned long new_vector;
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unsigned long flags;
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volatile unsigned int *vector
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= ((volatile unsigned int *)(KERNELBASE+0x100));
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if (nr < 1 || nr > 3)
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return;
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if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346);
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local_irq_save(flags);
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local_irq_disable();
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/* Save reset vector */
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save_vector = *vector;
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/* Setup fake reset vector that does
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* b .pmac_secondary_start - KERNELBASE
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*/
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switch(nr) {
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case 1:
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new_vector = (unsigned long)pmac_secondary_start_1;
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break;
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case 2:
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new_vector = (unsigned long)pmac_secondary_start_2;
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break;
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case 3:
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default:
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new_vector = (unsigned long)pmac_secondary_start_3;
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break;
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}
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*vector = 0x48000002 + (new_vector - KERNELBASE);
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/* flush data cache and inval instruction cache */
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flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
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/* Put some life in our friend */
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pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
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paca[nr].cpu_start = 1;
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/* FIXME: We wait a bit for the CPU to take the exception, I should
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* instead wait for the entry code to set something for me. Well,
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* ideally, all that crap will be done in prom.c and the CPU left
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* in a RAM-based wait loop like CHRP.
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*/
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for (j = 1; j < 1000000; j++)
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mb();
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/* Restore our exception vector */
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*vector = save_vector;
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flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
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local_irq_restore(flags);
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if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
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}
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static void __init smp_core99_setup_cpu(int cpu_nr)
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{
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/* Setup MPIC */
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mpic_setup_this_cpu();
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if (cpu_nr == 0) {
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extern void g5_phy_disable_cpu1(void);
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/* If we didn't start the second CPU, we must take
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* it off the bus
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*/
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if (num_online_cpus() < 2)
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g5_phy_disable_cpu1();
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if (ppc_md.progress) ppc_md.progress("smp_core99_setup_cpu 0 done", 0x349);
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}
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}
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struct smp_ops_t core99_smp_ops __pmacdata = {
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.message_pass = smp_mpic_message_pass,
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.probe = smp_core99_probe,
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.kick_cpu = smp_core99_kick_cpu,
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.setup_cpu = smp_core99_setup_cpu,
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.give_timebase = smp_generic_give_timebase,
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.take_timebase = smp_generic_take_timebase,
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};
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void __init pmac_setup_smp(void)
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{
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smp_ops = &core99_smp_ops;
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#ifdef CONFIG_HOTPLUG_CPU
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smp_ops->cpu_enable = generic_cpu_enable;
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smp_ops->cpu_disable = generic_cpu_disable;
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smp_ops->cpu_die = generic_cpu_die;
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#endif
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}
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