770 lines
18 KiB
C
770 lines
18 KiB
C
/*
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* Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
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* Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
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*
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* This driver is a port from stlc45xx:
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* Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/firmware.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/spi/spi.h>
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#include <linux/etherdevice.h>
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#include <linux/gpio.h>
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#include "p54spi.h"
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#include "p54spi_eeprom.h"
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#include "p54.h"
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#include "p54common.h"
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MODULE_FIRMWARE("3826.arm");
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MODULE_ALIAS("stlc45xx");
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/*
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* gpios should be handled in board files and provided via platform data,
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* but because it's currently impossible for p54spi to have a header file
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* in include/linux, let's use module paramaters for now
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*/
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static int p54spi_gpio_power = 97;
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module_param(p54spi_gpio_power, int, 0444);
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MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
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static int p54spi_gpio_irq = 87;
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module_param(p54spi_gpio_irq, int, 0444);
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MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
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static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
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void *buf, size_t len)
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{
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struct spi_transfer t[2];
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struct spi_message m;
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__le16 addr;
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/* We first push the address */
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addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = &addr;
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t[0].len = sizeof(addr);
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spi_message_add_tail(&t[0], &m);
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t[1].rx_buf = buf;
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t[1].len = len;
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spi_message_add_tail(&t[1], &m);
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spi_sync(priv->spi, &m);
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}
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static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
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const void *buf, size_t len)
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{
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struct spi_transfer t[3];
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struct spi_message m;
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__le16 addr;
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/* We first push the address */
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addr = cpu_to_le16(address << 8);
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spi_message_init(&m);
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memset(t, 0, sizeof(t));
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t[0].tx_buf = &addr;
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t[0].len = sizeof(addr);
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spi_message_add_tail(&t[0], &m);
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t[1].tx_buf = buf;
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t[1].len = len & ~1;
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spi_message_add_tail(&t[1], &m);
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if (len % 2) {
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__le16 last_word;
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last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
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t[2].tx_buf = &last_word;
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t[2].len = sizeof(last_word);
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spi_message_add_tail(&t[2], &m);
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}
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spi_sync(priv->spi, &m);
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}
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static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
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{
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__le16 val;
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p54spi_spi_read(priv, addr, &val, sizeof(val));
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return le16_to_cpu(val);
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}
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static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
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{
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__le32 val;
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p54spi_spi_read(priv, addr, &val, sizeof(val));
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return le32_to_cpu(val);
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}
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static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
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{
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p54spi_spi_write(priv, addr, &val, sizeof(val));
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}
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static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
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{
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p54spi_spi_write(priv, addr, &val, sizeof(val));
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}
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struct p54spi_spi_reg {
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u16 address; /* __le16 ? */
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u16 length;
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char *name;
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};
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static const struct p54spi_spi_reg p54spi_registers_array[] =
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{
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{ SPI_ADRS_ARM_INTERRUPTS, 32, "ARM_INT " },
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{ SPI_ADRS_ARM_INT_EN, 32, "ARM_INT_ENA " },
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{ SPI_ADRS_HOST_INTERRUPTS, 32, "HOST_INT " },
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{ SPI_ADRS_HOST_INT_EN, 32, "HOST_INT_ENA" },
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{ SPI_ADRS_HOST_INT_ACK, 32, "HOST_INT_ACK" },
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{ SPI_ADRS_GEN_PURP_1, 32, "GP1_COMM " },
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{ SPI_ADRS_GEN_PURP_2, 32, "GP2_COMM " },
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{ SPI_ADRS_DEV_CTRL_STAT, 32, "DEV_CTRL_STA" },
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{ SPI_ADRS_DMA_DATA, 16, "DMA_DATA " },
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{ SPI_ADRS_DMA_WRITE_CTRL, 16, "DMA_WR_CTRL " },
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{ SPI_ADRS_DMA_WRITE_LEN, 16, "DMA_WR_LEN " },
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{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_WR_BASE " },
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{ SPI_ADRS_DMA_READ_CTRL, 16, "DMA_RD_CTRL " },
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{ SPI_ADRS_DMA_READ_LEN, 16, "DMA_RD_LEN " },
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{ SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_RD_BASE " }
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};
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static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
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{
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int i;
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for (i = 0; i < 2000; i++) {
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__le32 buffer = p54spi_read32(priv, reg);
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if ((buffer & bits) == bits)
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return 1;
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}
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return 0;
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}
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static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
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const void *buf, size_t len)
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{
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if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
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cpu_to_le32(HOST_ALLOWED))) {
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dev_err(&priv->spi->dev, "spi_write_dma not allowed "
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"to DMA write.\n");
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return -EAGAIN;
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}
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p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
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cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
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p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
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p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
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p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
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return 0;
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}
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static int p54spi_request_firmware(struct ieee80211_hw *dev)
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{
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struct p54s_priv *priv = dev->priv;
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int ret;
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/* FIXME: should driver use it's own struct device? */
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ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
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if (ret < 0) {
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dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
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return ret;
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}
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ret = p54_parse_firmware(dev, priv->firmware);
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if (ret) {
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release_firmware(priv->firmware);
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return ret;
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}
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return 0;
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}
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static int p54spi_request_eeprom(struct ieee80211_hw *dev)
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{
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struct p54s_priv *priv = dev->priv;
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const struct firmware *eeprom;
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int ret;
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/*
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* allow users to customize their eeprom.
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*/
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ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
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if (ret < 0) {
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dev_info(&priv->spi->dev, "loading default eeprom...\n");
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ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
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sizeof(p54spi_eeprom));
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} else {
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dev_info(&priv->spi->dev, "loading user eeprom...\n");
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ret = p54_parse_eeprom(dev, (void *) eeprom->data,
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(int)eeprom->size);
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release_firmware(eeprom);
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}
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return ret;
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}
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static int p54spi_upload_firmware(struct ieee80211_hw *dev)
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{
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struct p54s_priv *priv = dev->priv;
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unsigned long fw_len, _fw_len;
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unsigned int offset = 0;
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int err = 0;
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u8 *fw;
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fw_len = priv->firmware->size;
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fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
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if (!fw)
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return -ENOMEM;
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/* stop the device */
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p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
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SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
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SPI_CTRL_STAT_START_HALTED));
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msleep(TARGET_BOOT_SLEEP);
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p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
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SPI_CTRL_STAT_HOST_OVERRIDE |
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SPI_CTRL_STAT_START_HALTED));
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msleep(TARGET_BOOT_SLEEP);
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while (fw_len > 0) {
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_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
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err = p54spi_spi_write_dma(priv, cpu_to_le32(
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ISL38XX_DEV_FIRMWARE_ADDR + offset),
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(fw + offset), _fw_len);
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if (err < 0)
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goto out;
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fw_len -= _fw_len;
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offset += _fw_len;
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}
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BUG_ON(fw_len != 0);
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/* enable host interrupts */
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p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
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cpu_to_le32(SPI_HOST_INTS_DEFAULT));
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/* boot the device */
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p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
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SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
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SPI_CTRL_STAT_RAM_BOOT));
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msleep(TARGET_BOOT_SLEEP);
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p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
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SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
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msleep(TARGET_BOOT_SLEEP);
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out:
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kfree(fw);
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return err;
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}
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static void p54spi_power_off(struct p54s_priv *priv)
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{
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disable_irq(gpio_to_irq(p54spi_gpio_irq));
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gpio_set_value(p54spi_gpio_power, 0);
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}
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static void p54spi_power_on(struct p54s_priv *priv)
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{
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gpio_set_value(p54spi_gpio_power, 1);
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enable_irq(gpio_to_irq(p54spi_gpio_irq));
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/*
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* need to wait a while before device can be accessed, the lenght
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* is just a guess
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*/
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msleep(10);
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}
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static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
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{
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p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
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}
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static int p54spi_wakeup(struct p54s_priv *priv)
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{
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/* wake the chip */
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p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
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cpu_to_le32(SPI_TARGET_INT_WAKEUP));
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/* And wait for the READY interrupt */
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if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
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cpu_to_le32(SPI_HOST_INT_READY))) {
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dev_err(&priv->spi->dev, "INT_READY timeout\n");
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return -EBUSY;
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}
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p54spi_int_ack(priv, SPI_HOST_INT_READY);
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return 0;
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}
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static inline void p54spi_sleep(struct p54s_priv *priv)
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{
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p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
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cpu_to_le32(SPI_TARGET_INT_SLEEP));
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}
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static void p54spi_int_ready(struct p54s_priv *priv)
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{
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p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
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SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
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switch (priv->fw_state) {
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case FW_STATE_BOOTING:
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priv->fw_state = FW_STATE_READY;
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complete(&priv->fw_comp);
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break;
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case FW_STATE_RESETTING:
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priv->fw_state = FW_STATE_READY;
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/* TODO: reinitialize state */
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break;
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default:
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break;
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}
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}
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static int p54spi_rx(struct p54s_priv *priv)
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{
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struct sk_buff *skb;
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u16 len;
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u16 rx_head[2];
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#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
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if (p54spi_wakeup(priv) < 0)
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return -EBUSY;
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/* Read data size and first data word in one SPI transaction
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* This is workaround for firmware/DMA bug,
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* when first data word gets lost under high load.
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*/
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p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
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len = rx_head[0];
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if (len == 0) {
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p54spi_sleep(priv);
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dev_err(&priv->spi->dev, "rx request of zero bytes\n");
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return 0;
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}
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/* Firmware may insert up to 4 padding bytes after the lmac header,
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* but it does not amend the size of SPI data transfer.
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* Such packets has correct data size in header, thus referencing
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* past the end of allocated skb. Reserve extra 4 bytes for this case */
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skb = dev_alloc_skb(len + 4);
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if (!skb) {
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p54spi_sleep(priv);
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dev_err(&priv->spi->dev, "could not alloc skb");
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return -ENOMEM;
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}
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if (len <= READAHEAD_SZ) {
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memcpy(skb_put(skb, len), rx_head + 1, len);
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} else {
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memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
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p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
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skb_put(skb, len - READAHEAD_SZ),
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len - READAHEAD_SZ);
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}
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p54spi_sleep(priv);
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/* Put additional bytes to compensate for the possible
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* alignment-caused truncation */
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skb_put(skb, 4);
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if (p54_rx(priv->hw, skb) == 0)
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dev_kfree_skb(skb);
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return 0;
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}
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static irqreturn_t p54spi_interrupt(int irq, void *config)
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{
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struct spi_device *spi = config;
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struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
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queue_work(priv->hw->workqueue, &priv->work);
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return IRQ_HANDLED;
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}
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static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
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{
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struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
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int ret = 0;
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if (p54spi_wakeup(priv) < 0)
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return -EBUSY;
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ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
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if (ret < 0)
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goto out;
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if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
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cpu_to_le32(SPI_HOST_INT_WR_READY))) {
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dev_err(&priv->spi->dev, "WR_READY timeout\n");
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ret = -EAGAIN;
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goto out;
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}
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p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
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if (FREE_AFTER_TX(skb))
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p54_free_skb(priv->hw, skb);
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out:
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p54spi_sleep(priv);
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return ret;
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}
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static int p54spi_wq_tx(struct p54s_priv *priv)
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{
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struct p54s_tx_info *entry;
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struct sk_buff *skb;
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struct ieee80211_tx_info *info;
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struct p54_tx_info *minfo;
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struct p54s_tx_info *dinfo;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&priv->tx_lock, flags);
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while (!list_empty(&priv->tx_pending)) {
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entry = list_entry(priv->tx_pending.next,
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struct p54s_tx_info, tx_list);
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list_del_init(&entry->tx_list);
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spin_unlock_irqrestore(&priv->tx_lock, flags);
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dinfo = container_of((void *) entry, struct p54s_tx_info,
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tx_list);
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minfo = container_of((void *) dinfo, struct p54_tx_info,
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data);
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info = container_of((void *) minfo, struct ieee80211_tx_info,
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rate_driver_data);
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skb = container_of((void *) info, struct sk_buff, cb);
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ret = p54spi_tx_frame(priv, skb);
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if (ret < 0) {
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p54_free_skb(priv->hw, skb);
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return ret;
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}
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spin_lock_irqsave(&priv->tx_lock, flags);
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}
|
|
spin_unlock_irqrestore(&priv->tx_lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
|
|
{
|
|
struct p54s_priv *priv = dev->priv;
|
|
struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
|
|
struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
|
|
struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
|
|
unsigned long flags;
|
|
|
|
BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
|
|
|
|
spin_lock_irqsave(&priv->tx_lock, flags);
|
|
list_add_tail(&di->tx_list, &priv->tx_pending);
|
|
spin_unlock_irqrestore(&priv->tx_lock, flags);
|
|
|
|
queue_work(priv->hw->workqueue, &priv->work);
|
|
}
|
|
|
|
static void p54spi_work(struct work_struct *work)
|
|
{
|
|
struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
|
|
u32 ints;
|
|
int ret;
|
|
|
|
mutex_lock(&priv->mutex);
|
|
|
|
if (priv->fw_state == FW_STATE_OFF)
|
|
goto out;
|
|
|
|
ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
|
|
|
|
if (ints & SPI_HOST_INT_READY) {
|
|
p54spi_int_ready(priv);
|
|
p54spi_int_ack(priv, SPI_HOST_INT_READY);
|
|
}
|
|
|
|
if (priv->fw_state != FW_STATE_READY)
|
|
goto out;
|
|
|
|
if (ints & SPI_HOST_INT_UPDATE) {
|
|
p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
|
|
ret = p54spi_rx(priv);
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
if (ints & SPI_HOST_INT_SW_UPDATE) {
|
|
p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
|
|
ret = p54spi_rx(priv);
|
|
if (ret < 0)
|
|
goto out;
|
|
}
|
|
|
|
ret = p54spi_wq_tx(priv);
|
|
out:
|
|
mutex_unlock(&priv->mutex);
|
|
}
|
|
|
|
static int p54spi_op_start(struct ieee80211_hw *dev)
|
|
{
|
|
struct p54s_priv *priv = dev->priv;
|
|
unsigned long timeout;
|
|
int ret = 0;
|
|
|
|
if (mutex_lock_interruptible(&priv->mutex)) {
|
|
ret = -EINTR;
|
|
goto out;
|
|
}
|
|
|
|
priv->fw_state = FW_STATE_BOOTING;
|
|
|
|
p54spi_power_on(priv);
|
|
|
|
ret = p54spi_upload_firmware(dev);
|
|
if (ret < 0) {
|
|
p54spi_power_off(priv);
|
|
goto out_unlock;
|
|
}
|
|
|
|
mutex_unlock(&priv->mutex);
|
|
|
|
timeout = msecs_to_jiffies(2000);
|
|
timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
|
|
timeout);
|
|
if (!timeout) {
|
|
dev_err(&priv->spi->dev, "firmware boot failed");
|
|
p54spi_power_off(priv);
|
|
ret = -1;
|
|
goto out;
|
|
}
|
|
|
|
if (mutex_lock_interruptible(&priv->mutex)) {
|
|
ret = -EINTR;
|
|
p54spi_power_off(priv);
|
|
goto out;
|
|
}
|
|
|
|
WARN_ON(priv->fw_state != FW_STATE_READY);
|
|
|
|
out_unlock:
|
|
mutex_unlock(&priv->mutex);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void p54spi_op_stop(struct ieee80211_hw *dev)
|
|
{
|
|
struct p54s_priv *priv = dev->priv;
|
|
unsigned long flags;
|
|
|
|
if (mutex_lock_interruptible(&priv->mutex)) {
|
|
/* FIXME: how to handle this error? */
|
|
return;
|
|
}
|
|
|
|
WARN_ON(priv->fw_state != FW_STATE_READY);
|
|
|
|
cancel_work_sync(&priv->work);
|
|
|
|
p54spi_power_off(priv);
|
|
spin_lock_irqsave(&priv->tx_lock, flags);
|
|
INIT_LIST_HEAD(&priv->tx_pending);
|
|
spin_unlock_irqrestore(&priv->tx_lock, flags);
|
|
|
|
priv->fw_state = FW_STATE_OFF;
|
|
mutex_unlock(&priv->mutex);
|
|
}
|
|
|
|
static int __devinit p54spi_probe(struct spi_device *spi)
|
|
{
|
|
struct p54s_priv *priv = NULL;
|
|
struct ieee80211_hw *hw;
|
|
int ret = -EINVAL;
|
|
|
|
hw = p54_init_common(sizeof(*priv));
|
|
if (!hw) {
|
|
dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
priv = hw->priv;
|
|
priv->hw = hw;
|
|
dev_set_drvdata(&spi->dev, priv);
|
|
priv->spi = spi;
|
|
|
|
spi->bits_per_word = 16;
|
|
spi->max_speed_hz = 24000000;
|
|
|
|
ret = spi_setup(spi);
|
|
if (ret < 0) {
|
|
dev_err(&priv->spi->dev, "spi_setup failed");
|
|
goto err_free_common;
|
|
}
|
|
|
|
ret = gpio_request(p54spi_gpio_power, "p54spi power");
|
|
if (ret < 0) {
|
|
dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
|
|
goto err_free_common;
|
|
}
|
|
|
|
ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
|
|
if (ret < 0) {
|
|
dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
|
|
goto err_free_common;
|
|
}
|
|
|
|
gpio_direction_output(p54spi_gpio_power, 0);
|
|
gpio_direction_input(p54spi_gpio_irq);
|
|
|
|
ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
|
|
p54spi_interrupt, IRQF_DISABLED, "p54spi",
|
|
priv->spi);
|
|
if (ret < 0) {
|
|
dev_err(&priv->spi->dev, "request_irq() failed");
|
|
goto err_free_common;
|
|
}
|
|
|
|
set_irq_type(gpio_to_irq(p54spi_gpio_irq),
|
|
IRQ_TYPE_EDGE_RISING);
|
|
|
|
disable_irq(gpio_to_irq(p54spi_gpio_irq));
|
|
|
|
INIT_WORK(&priv->work, p54spi_work);
|
|
init_completion(&priv->fw_comp);
|
|
INIT_LIST_HEAD(&priv->tx_pending);
|
|
mutex_init(&priv->mutex);
|
|
SET_IEEE80211_DEV(hw, &spi->dev);
|
|
priv->common.open = p54spi_op_start;
|
|
priv->common.stop = p54spi_op_stop;
|
|
priv->common.tx = p54spi_op_tx;
|
|
|
|
ret = p54spi_request_firmware(hw);
|
|
if (ret < 0)
|
|
goto err_free_common;
|
|
|
|
ret = p54spi_request_eeprom(hw);
|
|
if (ret)
|
|
goto err_free_common;
|
|
|
|
ret = p54_register_common(hw, &priv->spi->dev);
|
|
if (ret)
|
|
goto err_free_common;
|
|
|
|
return 0;
|
|
|
|
err_free_common:
|
|
p54_free_common(priv->hw);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit p54spi_remove(struct spi_device *spi)
|
|
{
|
|
struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
|
|
|
|
ieee80211_unregister_hw(priv->hw);
|
|
|
|
free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
|
|
|
|
gpio_free(p54spi_gpio_power);
|
|
gpio_free(p54spi_gpio_irq);
|
|
release_firmware(priv->firmware);
|
|
|
|
mutex_destroy(&priv->mutex);
|
|
|
|
p54_free_common(priv->hw);
|
|
ieee80211_free_hw(priv->hw);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static struct spi_driver p54spi_driver = {
|
|
.driver = {
|
|
/* use cx3110x name because board-n800.c uses that for the
|
|
* SPI port */
|
|
.name = "cx3110x",
|
|
.bus = &spi_bus_type,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
|
|
.probe = p54spi_probe,
|
|
.remove = __devexit_p(p54spi_remove),
|
|
};
|
|
|
|
static int __init p54spi_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = spi_register_driver(&p54spi_driver);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "failed to register SPI driver: %d", ret);
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void __exit p54spi_exit(void)
|
|
{
|
|
spi_unregister_driver(&p54spi_driver);
|
|
}
|
|
|
|
module_init(p54spi_init);
|
|
module_exit(p54spi_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
|