cca3731e02
Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Arria10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Arria10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> |
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| dts | ||
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| Makefile | ||
| deflate_xip_data.sh | ||
| install.sh | ||