238 lines
6.0 KiB
C
238 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Broadcom Starfighter2 private context
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*
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* Copyright (C) 2014, Broadcom Corporation
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*/
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#ifndef __BCM_SF2_H
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#define __BCM_SF2_H
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/if_vlan.h>
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#include <linux/reset.h>
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#include <net/dsa.h>
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#include "bcm_sf2_regs.h"
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#include "b53/b53_priv.h"
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struct bcm_sf2_hw_params {
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u16 top_rev;
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u16 core_rev;
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u16 gphy_rev;
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u32 num_gphy;
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u8 num_acb_queue;
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u8 num_rgmii;
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u8 num_ports;
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u8 fcb_pause_override:1;
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u8 acb_packets_inflight:1;
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};
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#define BCM_SF2_REGS_NAME {\
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"core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
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}
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#define BCM_SF2_REGS_NUM 6
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struct bcm_sf2_port_status {
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phy_interface_t mode;
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unsigned int link;
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bool enabled;
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};
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struct bcm_sf2_cfp_priv {
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/* Mutex protecting concurrent accesses to the CFP registers */
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struct mutex lock;
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DECLARE_BITMAP(used, CFP_NUM_RULES);
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DECLARE_BITMAP(unique, CFP_NUM_RULES);
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unsigned int rules_cnt;
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struct list_head rules_list;
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};
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struct bcm_sf2_priv {
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/* Base registers, keep those in order with BCM_SF2_REGS_NAME */
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void __iomem *core;
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void __iomem *reg;
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void __iomem *intrl2_0;
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void __iomem *intrl2_1;
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void __iomem *fcb;
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void __iomem *acb;
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struct reset_control *rcdev;
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/* Register offsets indirection tables */
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u32 type;
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const u16 *reg_offsets;
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unsigned int core_reg_align;
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unsigned int num_cfp_rules;
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unsigned int num_crossbar_int_ports;
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/* spinlock protecting access to the indirect registers */
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spinlock_t indir_lock;
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int irq0;
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int irq1;
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u32 irq0_stat;
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u32 irq0_mask;
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u32 irq1_stat;
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u32 irq1_mask;
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/* Backing b53_device */
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struct b53_device *dev;
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struct bcm_sf2_hw_params hw_params;
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struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
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/* Mask of ports enabled for Wake-on-LAN */
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u32 wol_ports_mask;
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struct clk *clk;
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struct clk *clk_mdiv;
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/* MoCA port location */
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int moca_port;
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/* Bitmask of ports having an integrated PHY */
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unsigned int int_phy_mask;
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/* Master and slave MDIO bus controller */
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unsigned int indir_phy_mask;
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struct device_node *master_mii_dn;
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struct mii_bus *slave_mii_bus;
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struct mii_bus *master_mii_bus;
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/* Bitmask of ports needing BRCM tags */
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unsigned int brcm_tag_mask;
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/* CFP rules context */
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struct bcm_sf2_cfp_priv cfp;
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};
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static inline struct bcm_sf2_priv *bcm_sf2_to_priv(struct dsa_switch *ds)
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{
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struct b53_device *dev = ds->priv;
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return dev->priv;
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}
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static inline u32 bcm_sf2_mangle_addr(struct bcm_sf2_priv *priv, u32 off)
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{
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return off << priv->core_reg_align;
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}
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#define SF2_IO_MACRO(name) \
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static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
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{ \
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return readl_relaxed(priv->name + off); \
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} \
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static inline void name##_writel(struct bcm_sf2_priv *priv, \
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u32 val, u32 off) \
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{ \
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writel_relaxed(val, priv->name + off); \
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} \
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/* Accesses to 64-bits register requires us to latch the hi/lo pairs
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* using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
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* spinlock is automatically grabbed and released to provide relative
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* atomiticy with latched reads/writes.
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*/
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#define SF2_IO64_MACRO(name) \
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static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
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{ \
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u32 indir, dir; \
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spin_lock(&priv->indir_lock); \
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dir = name##_readl(priv, off); \
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indir = reg_readl(priv, REG_DIR_DATA_READ); \
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spin_unlock(&priv->indir_lock); \
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return (u64)indir << 32 | dir; \
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} \
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static inline void name##_writeq(struct bcm_sf2_priv *priv, u64 val, \
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u32 off) \
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{ \
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spin_lock(&priv->indir_lock); \
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reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
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name##_writel(priv, lower_32_bits(val), off); \
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spin_unlock(&priv->indir_lock); \
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}
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#define SWITCH_INTR_L2(which) \
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static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
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u32 mask) \
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{ \
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priv->irq##which##_mask &= ~(mask); \
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intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
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} \
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static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
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u32 mask) \
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{ \
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intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
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priv->irq##which##_mask |= (mask); \
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} \
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static inline u32 core_readl(struct bcm_sf2_priv *priv, u32 off)
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{
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u32 tmp = bcm_sf2_mangle_addr(priv, off);
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return readl_relaxed(priv->core + tmp);
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}
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static inline void core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off)
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{
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u32 tmp = bcm_sf2_mangle_addr(priv, off);
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writel_relaxed(val, priv->core + tmp);
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}
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static inline u32 reg_readl(struct bcm_sf2_priv *priv, u16 off)
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{
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return readl_relaxed(priv->reg + priv->reg_offsets[off]);
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}
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static inline void reg_writel(struct bcm_sf2_priv *priv, u32 val, u16 off)
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{
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writel_relaxed(val, priv->reg + priv->reg_offsets[off]);
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}
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SF2_IO64_MACRO(core);
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SF2_IO_MACRO(intrl2_0);
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SF2_IO_MACRO(intrl2_1);
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SF2_IO_MACRO(fcb);
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SF2_IO_MACRO(acb);
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SWITCH_INTR_L2(0);
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SWITCH_INTR_L2(1);
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static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
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{
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return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
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}
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static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
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{
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writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
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}
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/* RXNFC */
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int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
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struct ethtool_rxnfc *nfc, u32 *rule_locs);
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int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
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struct ethtool_rxnfc *nfc);
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int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv);
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void bcm_sf2_cfp_exit(struct dsa_switch *ds);
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int bcm_sf2_cfp_resume(struct dsa_switch *ds);
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void bcm_sf2_cfp_get_strings(struct dsa_switch *ds, int port,
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u32 stringset, uint8_t *data);
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void bcm_sf2_cfp_get_ethtool_stats(struct dsa_switch *ds, int port,
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uint64_t *data);
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int bcm_sf2_cfp_get_sset_count(struct dsa_switch *ds, int port, int sset);
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#endif /* __BCM_SF2_H */
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