937 lines
24 KiB
C
937 lines
24 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 Juergen Beisert
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation
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* 51 Franklin Street, Fifth Floor
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* Boston, MA 02110-1301, USA.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/types.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <mach/spi.h>
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#define DRIVER_NAME "spi_imx"
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0c
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#define MXC_RESET 0x1c
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/* generic defines to abstract from the different register layouts */
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#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
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#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
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struct spi_imx_config {
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unsigned int speed_hz;
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unsigned int bpw;
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unsigned int mode;
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u8 cs;
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};
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enum spi_imx_devtype {
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IMX1_CSPI,
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IMX21_CSPI,
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IMX27_CSPI,
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IMX31_CSPI,
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IMX35_CSPI, /* CSPI on all i.mx except above */
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IMX51_ECSPI, /* ECSPI on i.mx51 and later */
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};
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struct spi_imx_data;
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struct spi_imx_devtype_data {
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void (*intctrl)(struct spi_imx_data *, int);
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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void (*trigger)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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void (*reset)(struct spi_imx_data *);
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enum spi_imx_devtype devtype;
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};
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struct spi_imx_data {
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struct spi_bitbang bitbang;
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struct completion xfer_done;
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void *base;
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int irq;
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struct clk *clk;
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unsigned long spi_clk;
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unsigned int count;
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void (*tx)(struct spi_imx_data *);
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void (*rx)(struct spi_imx_data *);
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void *rx_buf;
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const void *tx_buf;
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unsigned int txfifo; /* number of words pushed in tx FIFO */
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struct spi_imx_devtype_data *devtype_data;
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int chipselect[0];
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};
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static inline int is_imx27_cspi(struct spi_imx_data *d)
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{
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return d->devtype_data->devtype == IMX27_CSPI;
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}
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static inline int is_imx35_cspi(struct spi_imx_data *d)
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{
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return d->devtype_data->devtype == IMX35_CSPI;
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}
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static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
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{
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return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
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}
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#define MXC_SPI_BUF_RX(type) \
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static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
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{ \
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unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
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\
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if (spi_imx->rx_buf) { \
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*(type *)spi_imx->rx_buf = val; \
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spi_imx->rx_buf += sizeof(type); \
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} \
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}
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#define MXC_SPI_BUF_TX(type) \
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static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
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{ \
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type val = 0; \
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\
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if (spi_imx->tx_buf) { \
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val = *(type *)spi_imx->tx_buf; \
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spi_imx->tx_buf += sizeof(type); \
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} \
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\
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spi_imx->count -= sizeof(type); \
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\
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writel(val, spi_imx->base + MXC_CSPITXDATA); \
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}
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MXC_SPI_BUF_RX(u8)
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MXC_SPI_BUF_TX(u8)
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MXC_SPI_BUF_RX(u16)
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MXC_SPI_BUF_TX(u16)
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MXC_SPI_BUF_RX(u32)
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MXC_SPI_BUF_TX(u32)
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/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
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* (which is currently not the case in this driver)
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*/
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static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
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256, 384, 512, 768, 1024};
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/* MX21, MX27 */
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static unsigned int spi_imx_clkdiv_1(unsigned int fin,
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unsigned int fspi, unsigned int max)
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{
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int i;
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for (i = 2; i < max; i++)
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if (fspi * mxc_clkdivs[i] >= fin)
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return i;
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return max;
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}
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/* MX1, MX31, MX35, MX51 CSPI */
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static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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unsigned int fspi)
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{
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int i, div = 4;
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for (i = 0; i < 7; i++) {
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if (fspi * div >= fin)
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return i;
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div <<= 1;
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}
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return 7;
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}
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#define MX51_ECSPI_CTRL 0x08
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#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
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#define MX51_ECSPI_CTRL_XCH (1 << 2)
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#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
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#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
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#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
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#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
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#define MX51_ECSPI_CTRL_BL_OFFSET 20
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#define MX51_ECSPI_CONFIG 0x0c
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#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define MX51_ECSPI_INT 0x10
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#define MX51_ECSPI_INT_TEEN (1 << 0)
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#define MX51_ECSPI_INT_RREN (1 << 3)
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#define MX51_ECSPI_STAT 0x18
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#define MX51_ECSPI_STAT_RR (1 << 3)
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/* MX51 eCSPI */
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static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi)
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{
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/*
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* there are two 4-bit dividers, the pre-divider divides by
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* $pre, the post-divider by 2^$post
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*/
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unsigned int pre, post;
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if (unlikely(fspi > fin))
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return 0;
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post = fls(fin) - fls(fspi);
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if (fin > fspi << post)
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post++;
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/* now we have: (fin <= fspi << post) with post being minimal */
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post = max(4U, post) - 4;
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if (unlikely(post > 0xf)) {
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pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
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__func__, fspi, fin);
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return 0xff;
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}
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pre = DIV_ROUND_UP(fin, fspi << post) - 1;
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pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
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__func__, fin, fspi, post, pre);
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return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
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(post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
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}
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static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned val = 0;
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if (enable & MXC_INT_TE)
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val |= MX51_ECSPI_INT_TEEN;
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if (enable & MXC_INT_RR)
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val |= MX51_ECSPI_INT_RREN;
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writel(val, spi_imx->base + MX51_ECSPI_INT);
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}
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static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
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{
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u32 reg;
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reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
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reg |= MX51_ECSPI_CTRL_XCH;
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writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
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}
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static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
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/*
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* The hardware seems to have a race condition when changing modes. The
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* current assumption is that the selection of the channel arrives
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* earlier in the hardware than the mode bits when they are written at
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* the same time.
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* So set master mode for all channels as we do not support slave mode.
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*/
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ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
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/* set clock speed */
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ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz);
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/* set chip select to use */
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ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
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ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
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cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
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if (config->mode & SPI_CPHA)
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cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
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if (config->mode & SPI_CPOL)
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cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
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if (config->mode & SPI_CS_HIGH)
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cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
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writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
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writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
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return 0;
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}
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static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
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}
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static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
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{
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/* drain receive buffer */
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while (mx51_ecspi_rx_available(spi_imx))
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readl(spi_imx->base + MXC_CSPIRXDATA);
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}
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#define MX31_INTREG_TEEN (1 << 0)
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#define MX31_INTREG_RREN (1 << 3)
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#define MX31_CSPICTRL_ENABLE (1 << 0)
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#define MX31_CSPICTRL_MASTER (1 << 1)
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#define MX31_CSPICTRL_XCH (1 << 2)
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#define MX31_CSPICTRL_POL (1 << 4)
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#define MX31_CSPICTRL_PHA (1 << 5)
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#define MX31_CSPICTRL_SSCTL (1 << 6)
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#define MX31_CSPICTRL_SSPOL (1 << 7)
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#define MX31_CSPICTRL_BC_SHIFT 8
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#define MX35_CSPICTRL_BL_SHIFT 20
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#define MX31_CSPICTRL_CS_SHIFT 24
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#define MX35_CSPICTRL_CS_SHIFT 12
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#define MX31_CSPICTRL_DR_SHIFT 16
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#define MX31_CSPISTATUS 0x14
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#define MX31_STATUS_RR (1 << 3)
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/* These functions also work for the i.MX35, but be aware that
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* the i.MX35 has a slightly different register layout for bits
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* we do not use here.
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*/
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static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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if (enable & MXC_INT_TE)
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val |= MX31_INTREG_TEEN;
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if (enable & MXC_INT_RR)
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val |= MX31_INTREG_RREN;
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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reg = readl(spi_imx->base + MXC_CSPICTRL);
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reg |= MX31_CSPICTRL_XCH;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX31_CSPICTRL_DR_SHIFT;
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if (is_imx35_cspi(spi_imx)) {
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reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
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reg |= MX31_CSPICTRL_SSCTL;
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} else {
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reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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}
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if (config->mode & SPI_CPHA)
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reg |= MX31_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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reg |= MX31_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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reg |= MX31_CSPICTRL_SSPOL;
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if (cs < 0)
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reg |= (cs + 32) <<
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(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
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MX31_CSPICTRL_CS_SHIFT);
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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return 0;
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}
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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}
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static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
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{
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/* drain receive buffer */
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while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
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readl(spi_imx->base + MXC_CSPIRXDATA);
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}
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#define MX21_INTREG_RR (1 << 4)
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#define MX21_INTREG_TEEN (1 << 9)
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#define MX21_INTREG_RREN (1 << 13)
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#define MX21_CSPICTRL_POL (1 << 5)
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#define MX21_CSPICTRL_PHA (1 << 6)
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#define MX21_CSPICTRL_SSPOL (1 << 8)
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#define MX21_CSPICTRL_XCH (1 << 9)
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#define MX21_CSPICTRL_ENABLE (1 << 10)
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#define MX21_CSPICTRL_MASTER (1 << 11)
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#define MX21_CSPICTRL_DR_SHIFT 14
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#define MX21_CSPICTRL_CS_SHIFT 19
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static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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if (enable & MXC_INT_TE)
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val |= MX21_INTREG_TEEN;
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if (enable & MXC_INT_RR)
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val |= MX21_INTREG_RREN;
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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reg = readl(spi_imx->base + MXC_CSPICTRL);
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reg |= MX21_CSPICTRL_XCH;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
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reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
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MX21_CSPICTRL_DR_SHIFT;
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reg |= config->bpw - 1;
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if (config->mode & SPI_CPHA)
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reg |= MX21_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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reg |= MX21_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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reg |= MX21_CSPICTRL_SSPOL;
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if (cs < 0)
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reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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return 0;
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}
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static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
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}
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static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
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{
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writel(1, spi_imx->base + MXC_RESET);
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}
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#define MX1_INTREG_RR (1 << 3)
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#define MX1_INTREG_TEEN (1 << 8)
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#define MX1_INTREG_RREN (1 << 11)
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#define MX1_CSPICTRL_POL (1 << 4)
|
|
#define MX1_CSPICTRL_PHA (1 << 5)
|
|
#define MX1_CSPICTRL_XCH (1 << 8)
|
|
#define MX1_CSPICTRL_ENABLE (1 << 9)
|
|
#define MX1_CSPICTRL_MASTER (1 << 10)
|
|
#define MX1_CSPICTRL_DR_SHIFT 13
|
|
|
|
static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|
{
|
|
unsigned int val = 0;
|
|
|
|
if (enable & MXC_INT_TE)
|
|
val |= MX1_INTREG_TEEN;
|
|
if (enable & MXC_INT_RR)
|
|
val |= MX1_INTREG_RREN;
|
|
|
|
writel(val, spi_imx->base + MXC_CSPIINT);
|
|
}
|
|
|
|
static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
|
|
{
|
|
unsigned int reg;
|
|
|
|
reg = readl(spi_imx->base + MXC_CSPICTRL);
|
|
reg |= MX1_CSPICTRL_XCH;
|
|
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
|
}
|
|
|
|
static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
|
|
struct spi_imx_config *config)
|
|
{
|
|
unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
|
|
|
|
reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
|
|
MX1_CSPICTRL_DR_SHIFT;
|
|
reg |= config->bpw - 1;
|
|
|
|
if (config->mode & SPI_CPHA)
|
|
reg |= MX1_CSPICTRL_PHA;
|
|
if (config->mode & SPI_CPOL)
|
|
reg |= MX1_CSPICTRL_POL;
|
|
|
|
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
|
|
{
|
|
return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
|
|
}
|
|
|
|
static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
|
|
{
|
|
writel(1, spi_imx->base + MXC_RESET);
|
|
}
|
|
|
|
static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
|
|
.intctrl = mx1_intctrl,
|
|
.config = mx1_config,
|
|
.trigger = mx1_trigger,
|
|
.rx_available = mx1_rx_available,
|
|
.reset = mx1_reset,
|
|
.devtype = IMX1_CSPI,
|
|
};
|
|
|
|
static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
|
|
.intctrl = mx21_intctrl,
|
|
.config = mx21_config,
|
|
.trigger = mx21_trigger,
|
|
.rx_available = mx21_rx_available,
|
|
.reset = mx21_reset,
|
|
.devtype = IMX21_CSPI,
|
|
};
|
|
|
|
static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
|
|
/* i.mx27 cspi shares the functions with i.mx21 one */
|
|
.intctrl = mx21_intctrl,
|
|
.config = mx21_config,
|
|
.trigger = mx21_trigger,
|
|
.rx_available = mx21_rx_available,
|
|
.reset = mx21_reset,
|
|
.devtype = IMX27_CSPI,
|
|
};
|
|
|
|
static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
|
|
.intctrl = mx31_intctrl,
|
|
.config = mx31_config,
|
|
.trigger = mx31_trigger,
|
|
.rx_available = mx31_rx_available,
|
|
.reset = mx31_reset,
|
|
.devtype = IMX31_CSPI,
|
|
};
|
|
|
|
static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
|
|
/* i.mx35 and later cspi shares the functions with i.mx31 one */
|
|
.intctrl = mx31_intctrl,
|
|
.config = mx31_config,
|
|
.trigger = mx31_trigger,
|
|
.rx_available = mx31_rx_available,
|
|
.reset = mx31_reset,
|
|
.devtype = IMX35_CSPI,
|
|
};
|
|
|
|
static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
|
|
.intctrl = mx51_ecspi_intctrl,
|
|
.config = mx51_ecspi_config,
|
|
.trigger = mx51_ecspi_trigger,
|
|
.rx_available = mx51_ecspi_rx_available,
|
|
.reset = mx51_ecspi_reset,
|
|
.devtype = IMX51_ECSPI,
|
|
};
|
|
|
|
static struct platform_device_id spi_imx_devtype[] = {
|
|
{
|
|
.name = "imx1-cspi",
|
|
.driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
|
|
}, {
|
|
.name = "imx21-cspi",
|
|
.driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
|
|
}, {
|
|
.name = "imx27-cspi",
|
|
.driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
|
|
}, {
|
|
.name = "imx31-cspi",
|
|
.driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
|
|
}, {
|
|
.name = "imx35-cspi",
|
|
.driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
|
|
}, {
|
|
.name = "imx51-ecspi",
|
|
.driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static const struct of_device_id spi_imx_dt_ids[] = {
|
|
{ .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
|
|
{ .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
|
|
{ .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
|
|
{ .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
|
|
{ .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
|
|
{ .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static void spi_imx_chipselect(struct spi_device *spi, int is_active)
|
|
{
|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
|
int gpio = spi_imx->chipselect[spi->chip_select];
|
|
int active = is_active != BITBANG_CS_INACTIVE;
|
|
int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
|
|
|
|
if (gpio < 0)
|
|
return;
|
|
|
|
gpio_set_value(gpio, dev_is_lowactive ^ active);
|
|
}
|
|
|
|
static void spi_imx_push(struct spi_imx_data *spi_imx)
|
|
{
|
|
while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
|
|
if (!spi_imx->count)
|
|
break;
|
|
spi_imx->tx(spi_imx);
|
|
spi_imx->txfifo++;
|
|
}
|
|
|
|
spi_imx->devtype_data->trigger(spi_imx);
|
|
}
|
|
|
|
static irqreturn_t spi_imx_isr(int irq, void *dev_id)
|
|
{
|
|
struct spi_imx_data *spi_imx = dev_id;
|
|
|
|
while (spi_imx->devtype_data->rx_available(spi_imx)) {
|
|
spi_imx->rx(spi_imx);
|
|
spi_imx->txfifo--;
|
|
}
|
|
|
|
if (spi_imx->count) {
|
|
spi_imx_push(spi_imx);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
if (spi_imx->txfifo) {
|
|
/* No data left to push, but still waiting for rx data,
|
|
* enable receive data available interrupt.
|
|
*/
|
|
spi_imx->devtype_data->intctrl(
|
|
spi_imx, MXC_INT_RR);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
spi_imx->devtype_data->intctrl(spi_imx, 0);
|
|
complete(&spi_imx->xfer_done);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int spi_imx_setupxfer(struct spi_device *spi,
|
|
struct spi_transfer *t)
|
|
{
|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
|
struct spi_imx_config config;
|
|
|
|
config.bpw = t ? t->bits_per_word : spi->bits_per_word;
|
|
config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
|
|
config.mode = spi->mode;
|
|
config.cs = spi->chip_select;
|
|
|
|
if (!config.speed_hz)
|
|
config.speed_hz = spi->max_speed_hz;
|
|
if (!config.bpw)
|
|
config.bpw = spi->bits_per_word;
|
|
if (!config.speed_hz)
|
|
config.speed_hz = spi->max_speed_hz;
|
|
|
|
/* Initialize the functions for transfer */
|
|
if (config.bpw <= 8) {
|
|
spi_imx->rx = spi_imx_buf_rx_u8;
|
|
spi_imx->tx = spi_imx_buf_tx_u8;
|
|
} else if (config.bpw <= 16) {
|
|
spi_imx->rx = spi_imx_buf_rx_u16;
|
|
spi_imx->tx = spi_imx_buf_tx_u16;
|
|
} else if (config.bpw <= 32) {
|
|
spi_imx->rx = spi_imx_buf_rx_u32;
|
|
spi_imx->tx = spi_imx_buf_tx_u32;
|
|
} else
|
|
BUG();
|
|
|
|
spi_imx->devtype_data->config(spi_imx, &config);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int spi_imx_transfer(struct spi_device *spi,
|
|
struct spi_transfer *transfer)
|
|
{
|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
|
|
|
spi_imx->tx_buf = transfer->tx_buf;
|
|
spi_imx->rx_buf = transfer->rx_buf;
|
|
spi_imx->count = transfer->len;
|
|
spi_imx->txfifo = 0;
|
|
|
|
init_completion(&spi_imx->xfer_done);
|
|
|
|
spi_imx_push(spi_imx);
|
|
|
|
spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
|
|
|
|
wait_for_completion(&spi_imx->xfer_done);
|
|
|
|
return transfer->len;
|
|
}
|
|
|
|
static int spi_imx_setup(struct spi_device *spi)
|
|
{
|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
|
int gpio = spi_imx->chipselect[spi->chip_select];
|
|
|
|
dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
|
|
spi->mode, spi->bits_per_word, spi->max_speed_hz);
|
|
|
|
if (gpio >= 0)
|
|
gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
|
|
|
|
spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void spi_imx_cleanup(struct spi_device *spi)
|
|
{
|
|
}
|
|
|
|
static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *np = pdev->dev.of_node;
|
|
const struct of_device_id *of_id =
|
|
of_match_device(spi_imx_dt_ids, &pdev->dev);
|
|
struct spi_imx_master *mxc_platform_info =
|
|
dev_get_platdata(&pdev->dev);
|
|
struct spi_master *master;
|
|
struct spi_imx_data *spi_imx;
|
|
struct resource *res;
|
|
int i, ret, num_cs;
|
|
|
|
if (!np && !mxc_platform_info) {
|
|
dev_err(&pdev->dev, "can't get the platform data\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
|
|
if (ret < 0)
|
|
num_cs = mxc_platform_info->num_chipselect;
|
|
|
|
master = spi_alloc_master(&pdev->dev,
|
|
sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = num_cs;
|
|
|
|
spi_imx = spi_master_get_devdata(master);
|
|
spi_imx->bitbang.master = spi_master_get(master);
|
|
|
|
for (i = 0; i < master->num_chipselect; i++) {
|
|
int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
|
|
if (cs_gpio < 0)
|
|
cs_gpio = mxc_platform_info->chipselect[i];
|
|
|
|
spi_imx->chipselect[i] = cs_gpio;
|
|
if (cs_gpio < 0)
|
|
continue;
|
|
|
|
ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
|
|
if (ret) {
|
|
while (i > 0) {
|
|
i--;
|
|
if (spi_imx->chipselect[i] >= 0)
|
|
gpio_free(spi_imx->chipselect[i]);
|
|
}
|
|
dev_err(&pdev->dev, "can't get cs gpios\n");
|
|
goto out_master_put;
|
|
}
|
|
}
|
|
|
|
spi_imx->bitbang.chipselect = spi_imx_chipselect;
|
|
spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
|
|
spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
|
|
spi_imx->bitbang.master->setup = spi_imx_setup;
|
|
spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
|
|
spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
init_completion(&spi_imx->xfer_done);
|
|
|
|
spi_imx->devtype_data = of_id ? of_id->data :
|
|
(struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "can't get platform resource\n");
|
|
ret = -ENOMEM;
|
|
goto out_gpio_free;
|
|
}
|
|
|
|
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
|
|
dev_err(&pdev->dev, "request_mem_region failed\n");
|
|
ret = -EBUSY;
|
|
goto out_gpio_free;
|
|
}
|
|
|
|
spi_imx->base = ioremap(res->start, resource_size(res));
|
|
if (!spi_imx->base) {
|
|
ret = -EINVAL;
|
|
goto out_release_mem;
|
|
}
|
|
|
|
spi_imx->irq = platform_get_irq(pdev, 0);
|
|
if (spi_imx->irq < 0) {
|
|
ret = -EINVAL;
|
|
goto out_iounmap;
|
|
}
|
|
|
|
ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
|
|
goto out_iounmap;
|
|
}
|
|
|
|
spi_imx->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(spi_imx->clk)) {
|
|
dev_err(&pdev->dev, "unable to get clock\n");
|
|
ret = PTR_ERR(spi_imx->clk);
|
|
goto out_free_irq;
|
|
}
|
|
|
|
clk_enable(spi_imx->clk);
|
|
spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
|
|
|
|
spi_imx->devtype_data->reset(spi_imx);
|
|
|
|
spi_imx->devtype_data->intctrl(spi_imx, 0);
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
ret = spi_bitbang_start(&spi_imx->bitbang);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
|
|
goto out_clk_put;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "probed\n");
|
|
|
|
return ret;
|
|
|
|
out_clk_put:
|
|
clk_disable(spi_imx->clk);
|
|
clk_put(spi_imx->clk);
|
|
out_free_irq:
|
|
free_irq(spi_imx->irq, spi_imx);
|
|
out_iounmap:
|
|
iounmap(spi_imx->base);
|
|
out_release_mem:
|
|
release_mem_region(res->start, resource_size(res));
|
|
out_gpio_free:
|
|
for (i = 0; i < master->num_chipselect; i++)
|
|
if (spi_imx->chipselect[i] >= 0)
|
|
gpio_free(spi_imx->chipselect[i]);
|
|
out_master_put:
|
|
spi_master_put(master);
|
|
kfree(master);
|
|
platform_set_drvdata(pdev, NULL);
|
|
return ret;
|
|
}
|
|
|
|
static int __devexit spi_imx_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
|
|
int i;
|
|
|
|
spi_bitbang_stop(&spi_imx->bitbang);
|
|
|
|
writel(0, spi_imx->base + MXC_CSPICTRL);
|
|
clk_disable(spi_imx->clk);
|
|
clk_put(spi_imx->clk);
|
|
free_irq(spi_imx->irq, spi_imx);
|
|
iounmap(spi_imx->base);
|
|
|
|
for (i = 0; i < master->num_chipselect; i++)
|
|
if (spi_imx->chipselect[i] >= 0)
|
|
gpio_free(spi_imx->chipselect[i]);
|
|
|
|
spi_master_put(master);
|
|
|
|
release_mem_region(res->start, resource_size(res));
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver spi_imx_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = spi_imx_dt_ids,
|
|
},
|
|
.id_table = spi_imx_devtype,
|
|
.probe = spi_imx_probe,
|
|
.remove = __devexit_p(spi_imx_remove),
|
|
};
|
|
module_platform_driver(spi_imx_driver);
|
|
|
|
MODULE_DESCRIPTION("SPI Master Controller driver");
|
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
|
MODULE_LICENSE("GPL");
|