530 lines
14 KiB
C
530 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2014 QLogic Corporation
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*/
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#ifndef __QLA_MR_H
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#define __QLA_MR_H
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#include "qla_dsd.h"
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/*
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* The PCI VendorID and DeviceID for our board.
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*/
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#define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001
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/* FX00 specific definitions */
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#define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */
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struct cmd_type_7_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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uint8_t reserved_0;
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uint8_t port_path_ctrl;
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uint16_t reserved_1;
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__le16 tgt_idx; /* Target Idx. */
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uint16_t timeout; /* Command timeout. */
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__le16 dseg_count; /* Data segment count. */
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uint8_t scsi_rsp_dsd_len;
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uint8_t reserved_2;
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struct scsi_lun lun; /* LUN (LE). */
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uint8_t cntrl_flags;
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uint8_t task_mgmt_flags; /* Task management flags. */
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uint8_t task;
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uint8_t crn;
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uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
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__le32 byte_count; /* Total byte count. */
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struct dsd64 dsd;
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};
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#define STATUS_TYPE_FX00 0x01 /* Status entry. */
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struct sts_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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uint32_t reserved_3; /* System handle. */
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__le16 comp_status; /* Completion status. */
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uint16_t reserved_0; /* OX_ID used by the firmware. */
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__le32 residual_len; /* FW calc residual transfer length. */
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uint16_t reserved_1;
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uint16_t state_flags; /* State flags. */
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uint16_t reserved_2;
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__le16 scsi_status; /* SCSI status. */
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uint32_t sense_len; /* FCP SENSE length. */
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uint8_t data[32]; /* FCP response/sense information. */
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};
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#define MAX_HANDLE_COUNT 15
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#define MULTI_STATUS_TYPE_FX00 0x0D
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struct multi_sts_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t handle_count;
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uint8_t entry_status;
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__le32 handles[MAX_HANDLE_COUNT];
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};
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#define TSK_MGMT_IOCB_TYPE_FX00 0x05
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struct tsk_mgmt_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define;
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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uint32_t reserved_0;
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__le16 tgt_id; /* Target Idx. */
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uint16_t reserved_1;
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uint16_t reserved_3;
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uint16_t reserved_4;
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struct scsi_lun lun; /* LUN (LE). */
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__le32 control_flags; /* Control Flags. */
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uint8_t reserved_2[32];
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};
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#define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */
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struct abort_iocb_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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__le32 reserved_0;
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__le16 tgt_id_sts; /* Completion status. */
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__le16 options;
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uint32_t abort_handle; /* System handle. */
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__le32 reserved_2;
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__le16 req_que_no;
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uint8_t reserved_1[38];
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};
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#define IOCTL_IOSB_TYPE_FX00 0x0C
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struct ioctl_iocb_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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uint32_t reserved_0; /* System handle. */
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uint16_t comp_func_num;
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__le16 fw_iotcl_flags;
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__le32 dataword_r; /* Data word returned */
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uint32_t adapid; /* Adapter ID */
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uint32_t dataword_r_extra;
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__le32 seq_no;
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uint8_t reserved_2[20];
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uint32_t residuallen;
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__le32 status;
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};
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#define STATUS_CONT_TYPE_FX00 0x04
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#define FX00_IOCB_TYPE 0x0B
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struct fxdisc_entry_fx00 {
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uint8_t entry_type; /* Entry type. */
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uint8_t entry_count; /* Entry count. */
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uint8_t sys_define; /* System Defined. */
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uint8_t entry_status; /* Entry Status. */
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uint32_t handle; /* System handle. */
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__le32 reserved_0; /* System handle. */
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__le16 func_num;
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__le16 req_xfrcnt;
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__le16 req_dsdcnt;
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__le16 rsp_xfrcnt;
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__le16 rsp_dsdcnt;
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uint8_t flags;
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uint8_t reserved_1;
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/*
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* Use array size 1 below to prevent that Coverity complains about
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* the append_dsd64() calls for the two arrays below.
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*/
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struct dsd64 dseg_rq[1];
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struct dsd64 dseg_rsp[1];
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__le32 dataword;
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__le32 adapid;
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__le32 adapid_hi;
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__le32 dataword_extra;
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};
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struct qlafx00_tgt_node_info {
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uint8_t tgt_node_wwpn[WWN_SIZE];
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uint8_t tgt_node_wwnn[WWN_SIZE];
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uint32_t tgt_node_state;
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uint8_t reserved[128];
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uint32_t reserved_1[8];
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uint64_t reserved_2[4];
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} __packed;
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#define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
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#define QLAFX00_LINK_STATUS_DOWN 0x10
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#define QLAFX00_LINK_STATUS_UP 0x11
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#define QLAFX00_PORT_SPEED_2G 0x2
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#define QLAFX00_PORT_SPEED_4G 0x4
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#define QLAFX00_PORT_SPEED_8G 0x8
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#define QLAFX00_PORT_SPEED_10G 0xa
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struct port_info_data {
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uint8_t port_state;
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uint8_t port_type;
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uint16_t port_identifier;
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uint32_t up_port_state;
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uint8_t fw_ver_num[32];
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uint8_t portal_attrib;
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uint16_t host_option;
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uint8_t reset_delay;
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uint8_t pdwn_retry_cnt;
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uint16_t max_luns2tgt;
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uint8_t risc_ver;
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uint8_t pconn_option;
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uint16_t risc_option;
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uint16_t max_frame_len;
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uint16_t max_iocb_alloc;
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uint16_t exec_throttle;
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uint8_t retry_cnt;
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uint8_t retry_delay;
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uint8_t port_name[8];
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uint8_t port_id[3];
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uint8_t link_status;
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uint8_t plink_rate;
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uint32_t link_config;
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uint16_t adap_haddr;
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uint8_t tgt_disc;
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uint8_t log_tout;
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uint8_t node_name[8];
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uint16_t erisc_opt1;
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uint8_t resp_acc_tmr;
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uint8_t intr_del_tmr;
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uint8_t erisc_opt2;
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uint8_t alt_port_name[8];
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uint8_t alt_node_name[8];
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uint8_t link_down_tout;
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uint8_t conn_type;
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uint8_t fc_fw_mode;
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uint32_t uiReserved[48];
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} __packed;
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/* OS Type Designations */
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#define OS_TYPE_UNKNOWN 0
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#define OS_TYPE_LINUX 2
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/* Linux Info */
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#define SYSNAME_LENGTH 128
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#define NODENAME_LENGTH 64
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#define RELEASE_LENGTH 64
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#define VERSION_LENGTH 64
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#define MACHINE_LENGTH 64
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#define DOMNAME_LENGTH 64
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struct host_system_info {
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uint32_t os_type;
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char sysname[SYSNAME_LENGTH];
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char nodename[NODENAME_LENGTH];
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char release[RELEASE_LENGTH];
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char version[VERSION_LENGTH];
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char machine[MACHINE_LENGTH];
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char domainname[DOMNAME_LENGTH];
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char hostdriver[VERSION_LENGTH];
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uint32_t reserved[64];
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} __packed;
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struct register_host_info {
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struct host_system_info hsi; /* host system info */
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uint64_t utc; /* UTC (system time) */
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uint32_t reserved[64]; /* future additions */
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} __packed;
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#define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
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#define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
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struct config_info_data {
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uint8_t model_num[16];
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uint8_t model_description[80];
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uint8_t reserved0[160];
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uint8_t symbolic_name[64];
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uint8_t serial_num[32];
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uint8_t hw_version[16];
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uint8_t fw_version[16];
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uint8_t uboot_version[16];
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uint8_t fru_serial_num[32];
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uint8_t fc_port_count;
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uint8_t iscsi_port_count;
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uint8_t reserved1[2];
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uint8_t mode;
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uint8_t log_level;
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uint8_t reserved2[2];
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uint32_t log_size;
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uint8_t tgt_pres_mode;
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uint8_t iqn_flags;
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uint8_t lun_mapping;
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uint64_t adapter_id;
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uint32_t cluster_key_len;
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uint8_t cluster_key[16];
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uint64_t cluster_master_id;
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uint64_t cluster_slave_id;
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uint8_t cluster_flags;
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uint32_t enabled_capabilities;
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uint32_t nominal_temp_value;
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} __packed;
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#define FXDISC_GET_CONFIG_INFO 0x01
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#define FXDISC_GET_PORT_INFO 0x02
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#define FXDISC_GET_TGT_NODE_INFO 0x80
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#define FXDISC_GET_TGT_NODE_LIST 0x81
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#define FXDISC_REG_HOST_INFO 0x99
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#define FXDISC_ABORT_IOCTL 0xff
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#define QLAFX00_HBA_ICNTRL_REG 0x20B08
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#define QLAFX00_ICR_ENB_MASK 0x80000000
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#define QLAFX00_ICR_DIS_MASK 0x7fffffff
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#define QLAFX00_HST_RST_REG 0x18264
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#define QLAFX00_SOC_TEMP_REG 0x184C4
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#define QLAFX00_HST_TO_HBA_REG 0x20A04
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#define QLAFX00_HBA_TO_HOST_REG 0x21B70
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#define QLAFX00_HST_INT_STS_BITS 0x7
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#define QLAFX00_BAR1_BASE_ADDR_REG 0x40018
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#define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
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#define QLAFX00_INTR_MB_CMPLT 0x1
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#define QLAFX00_INTR_RSP_CMPLT 0x2
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#define QLAFX00_INTR_ASYNC_CMPLT 0x4
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#define QLAFX00_MBA_SYSTEM_ERR 0x8002
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#define QLAFX00_MBA_TEMP_OVER 0x8005
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#define QLAFX00_MBA_TEMP_NORM 0x8006
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#define QLAFX00_MBA_TEMP_CRIT 0x8007
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#define QLAFX00_MBA_LINK_UP 0x8011
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#define QLAFX00_MBA_LINK_DOWN 0x8012
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#define QLAFX00_MBA_PORT_UPDATE 0x8014
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#define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062
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#define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800
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#define SOC_FABRIC_RST_CONTROL_REG 0x0020840
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#define SOC_FABRIC_CONTROL_REG 0x0020200
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#define SOC_FABRIC_CONFIG_REG 0x0020204
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#define SOC_PWR_MANAGEMENT_PWR_DOWN_REG 0x001820C
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#define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00
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#define SOC_CORE_TIMER_REG 0x0021850
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#define SOC_IRQ_ACK_REG 0x00218b4
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#define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */
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#define QLAFX00_SET_HST_INTR(ha, value) \
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wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
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value)
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#define QLAFX00_CLR_HST_INTR(ha, value) \
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wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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~value)
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#define QLAFX00_RD_INTR_REG(ha) \
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rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
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#define QLAFX00_CLR_INTR_REG(ha, value) \
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wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
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~value)
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#define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
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wrt_reg_dword((ha)->cregbase + off, val)
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#define QLAFX00_GET_HBA_SOC_REG(ha, off)\
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rd_reg_dword((ha)->cregbase + off)
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#define QLAFX00_HBA_RST_REG(ha, val)\
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wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
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#define QLAFX00_RD_ICNTRL_REG(ha) \
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rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
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#define QLAFX00_ENABLE_ICNTRL_REG(ha) \
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wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
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QLAFX00_ICR_ENB_MASK))
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#define QLAFX00_DISABLE_ICNTRL_REG(ha) \
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wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
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(QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
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QLAFX00_ICR_DIS_MASK))
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#define QLAFX00_RD_REG(ha, off) \
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rd_reg_dword((ha)->cregbase + off)
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#define QLAFX00_WR_REG(ha, off, val) \
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wrt_reg_dword((ha)->cregbase + off, val)
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struct qla_mt_iocb_rqst_fx00 {
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__le32 reserved_0;
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__le16 func_type;
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uint8_t flags;
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uint8_t reserved_1;
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__le32 dataword;
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__le32 adapid;
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__le32 adapid_hi;
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__le32 dataword_extra;
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__le16 req_len;
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__le16 reserved_2;
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__le16 rsp_len;
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__le16 reserved_3;
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};
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struct qla_mt_iocb_rsp_fx00 {
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uint32_t reserved_1;
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uint16_t func_type;
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__le16 ioctl_flags;
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__le32 ioctl_data;
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uint32_t adapid;
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uint32_t adapid_hi;
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uint32_t reserved_2;
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__le32 seq_number;
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uint8_t reserved_3[20];
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int32_t res_count;
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__le32 status;
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};
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#define MAILBOX_REGISTER_COUNT_FX00 16
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#define AEN_MAILBOX_REGISTER_COUNT_FX00 8
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#define MAX_FIBRE_DEVICES_FX00 512
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#define MAX_LUNS_FX00 0x1024
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#define MAX_TARGETS_FX00 MAX_ISA_DEVICES
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#define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */
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#define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
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/*
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* Firmware state codes for QLAFX00 adapters
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*/
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#define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue
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* Initialize FW Mbox cmd
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*/
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#define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by
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* the driver
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*/
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#define FX00_DEF_RATOV 10
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struct mr_data_fx00 {
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uint8_t symbolic_name[64];
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uint8_t serial_num[32];
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uint8_t hw_version[16];
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uint8_t fw_version[16];
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uint8_t uboot_version[16];
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uint8_t fru_serial_num[32];
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fc_port_t fcport; /* fcport used for requests
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* that are not linked
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* to a particular target
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*/
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uint8_t fw_hbt_en;
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uint8_t fw_hbt_cnt;
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uint8_t fw_hbt_miss_cnt;
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uint32_t old_fw_hbt_cnt;
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uint16_t fw_reset_timer_tick;
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uint8_t fw_reset_timer_exp;
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uint16_t fw_critemp_timer_tick;
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uint32_t old_aenmbx0_state;
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uint32_t critical_temperature;
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bool extended_io_enabled;
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bool host_info_resend;
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uint8_t hinfo_resend_timer_tick;
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};
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#define QLAFX00_EXTENDED_IO_EN_MASK 0x20
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/*
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* SoC Junction Temperature is stored in
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* bits 9:1 of SoC Junction Temperature Register
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* in a firmware specific format format.
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* To get the temperature in Celsius degrees
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* the value from this bitfiled should be converted
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* using this formula:
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* Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
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* where X is the bit field value
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|
* this macro reads the register, extracts the bitfield value,
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* performs the calcualtions and returns temperature in Celsius
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|
*/
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#define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
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((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
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|
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#define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */
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#define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */
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|
#define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */
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#define QLAFX00_RESET_INTERVAL 120 /* number of seconds */
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|
#define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */
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|
#define QLAFX00_CRITEMP_INTERVAL 60 /* number of seconds */
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|
#define QLAFX00_HINFO_RESEND_INTERVAL 60 /* number of seconds */
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|
|
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#define QLAFX00_CRITEMP_THRSHLD 80 /* Celsius degrees */
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|
|
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/* Max conncurrent IOs that can be queued */
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#define QLAFX00_MAX_CANQUEUE 1024
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|
|
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/* IOCTL IOCB abort success */
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#define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS 0x68
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#endif
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