138 lines
5.1 KiB
C
138 lines
5.1 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr_r352.h"
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#include "ls_ucode.h"
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#include <engine/falcon.h>
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/**
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* struct acr_r361_flcn_bl_desc - DMEM bootloader descriptor
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* @signature: 16B signature for secure code. 0s if no secure code
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* @ctx_dma: DMA context to be used by BL while loading code/data
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* @code_dma_base: 256B-aligned Physical FB Address where code is located
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* (falcon's $xcbase register)
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* @non_sec_code_off: offset from code_dma_base where the non-secure code is
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* located. The offset must be multiple of 256 to help perf
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* @non_sec_code_size: the size of the nonSecure code part.
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* @sec_code_off: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @sec_code_size: offset from code_dma_base where the secure code is
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* located. The offset must be multiple of 256 to help perf
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* @code_entry_point: code entry point which will be invoked by BL after
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* code is loaded.
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* @data_dma_base: 256B aligned Physical FB Address where data is located.
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* (falcon's $xdbase register)
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* @data_size: size of data block. Should be multiple of 256B
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*
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* Structure used by the bootloader to load the rest of the code. This has
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* to be filled by host and copied into DMEM at offset provided in the
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* hsflcn_bl_desc.bl_desc_dmem_load_off.
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*/
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struct acr_r361_flcn_bl_desc {
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u32 reserved[4];
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u32 signature[4];
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u32 ctx_dma;
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struct flcn_u64 code_dma_base;
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u32 non_sec_code_off;
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u32 non_sec_code_size;
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u32 sec_code_off;
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u32 sec_code_size;
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u32 code_entry_point;
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struct flcn_u64 data_dma_base;
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u32 data_size;
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};
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static void
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acr_r361_generate_flcn_bl_desc(const struct nvkm_acr *acr,
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const struct ls_ucode_img *img, u64 wpr_addr,
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void *_desc)
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{
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struct acr_r361_flcn_bl_desc *desc = _desc;
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const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;
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u64 base, addr_code, addr_data;
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base = wpr_addr + img->lsb_header.ucode_off + pdesc->app_start_offset;
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addr_code = base + pdesc->app_resident_code_offset;
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addr_data = base + pdesc->app_resident_data_offset;
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memset(desc, 0, sizeof(*desc));
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desc->ctx_dma = FALCON_DMAIDX_UCODE;
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desc->code_dma_base = u64_to_flcn64(addr_code);
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desc->non_sec_code_off = pdesc->app_resident_code_offset;
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desc->non_sec_code_size = pdesc->app_resident_code_size;
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desc->code_entry_point = pdesc->app_imem_entry;
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desc->data_dma_base = u64_to_flcn64(addr_data);
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desc->data_size = pdesc->app_resident_data_size;
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}
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static void
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acr_r361_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,
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u64 offset)
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{
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struct acr_r361_flcn_bl_desc *bl_desc = _bl_desc;
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memset(bl_desc, 0, sizeof(*bl_desc));
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bl_desc->ctx_dma = FALCON_DMAIDX_VIRT;
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bl_desc->code_dma_base = u64_to_flcn64(offset);
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bl_desc->non_sec_code_off = hdr->non_sec_code_off;
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bl_desc->non_sec_code_size = hdr->non_sec_code_size;
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bl_desc->sec_code_off = hdr->app[0].sec_code_off;
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bl_desc->sec_code_size = hdr->app[0].sec_code_size;
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bl_desc->code_entry_point = 0;
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bl_desc->data_dma_base = u64_to_flcn64(offset + hdr->data_dma_base);
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bl_desc->data_size = hdr->data_size;
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}
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const struct acr_r352_ls_func
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acr_r361_ls_fecs_func = {
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.load = acr_ls_ucode_load_fecs,
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.generate_bl_desc = acr_r361_generate_flcn_bl_desc,
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.bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc),
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};
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const struct acr_r352_ls_func
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acr_r361_ls_gpccs_func = {
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.load = acr_ls_ucode_load_gpccs,
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.generate_bl_desc = acr_r361_generate_flcn_bl_desc,
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.bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc),
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/* GPCCS will be loaded using PRI */
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.lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,
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};
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const struct acr_r352_func
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acr_r361_func = {
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.generate_hs_bl_desc = acr_r361_generate_hs_bl_desc,
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.hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc),
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.ls_func = {
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[NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func,
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[NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func,
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},
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};
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struct nvkm_acr *
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acr_r361_new(unsigned long managed_falcons)
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{
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return acr_r352_new_(&acr_r361_func, NVKM_SECBOOT_FALCON_PMU,
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managed_falcons);
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}
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